{"schema":"libjg2-1", "vpath":"/git/", "avatar":"/git/avatar/", "alang":"", "gen_ut":1752735387, "reponame":"openssl", "desc":"OpenSSL", "owner": { "name": "Andy Green", "email": "andy@warmcat.com", "md5": "c50933ca2aa61e0fe2c43d46bb6b59cb" },"url":"https://warmcat.com/repo/openssl", "f":3, "items": [ {"schema":"libjg2-1", "cid":"ca8f312ad8451b52645af84a33a25d4e", "commit": {"type":"commit", "time": 1486120910, "time_ofs": 60, "oid_tree": { "oid": "2f4395b9f20bb7cbda2e8e241af9cfe896882f9c", "alias": []}, "oid":{ "oid": "66bee01c822c5dd26679cad076c52b3d81199668", "alias": []}, "msg": "crypto/x86_64cpuid.pl: detect if kernel preserves %zmm registers.", "sig_commit": { "git_time": { "time": 1486120910, "offset": 60 }, "name": "Andy Polyakov", "email": "appro@openssl.org", "md5": "50bd64fa2a792cbbf679fa16213a3b2a" }, "sig_author": { "git_time": { "time": 1485540217, "offset": 60 }, "name": "Andy Polyakov", "email": "appro@openssl.org", "md5": "50bd64fa2a792cbbf679fa16213a3b2a" }}, "body": "crypto/x86_64cpuid.pl: detect if kernel preserves %zmm registers.\n\nReviewed-by: Rich Salz \u003crsalz@openssl.org\u003e\n" , "diff": "diff --git a/crypto/x86_64cpuid.pl b/crypto/x86_64cpuid.pl\nindex 6cb1521..3082253 100644\n--- a/crypto/x86_64cpuid.pl\n+++ b/crypto/x86_64cpuid.pl\n@@ -175,13 +175,21 @@ OPENSSL_ia32_cpuid:\n \tjnc\t.Lclear_avx\n \txor\t%ecx,%ecx\t\t# XCR0\n \t.byte\t0x0f,0x01,0xd0\t\t# xgetbv\n+\tand\t\u005c$0xe6,%eax\t\t# isolate XMM, YMM and ZMM state support\n+\tcmp\t\u005c$0xe6,%eax\n+\tje\t.Ldone\n+\tandl\t\u005c$0xfffeffff,8(%rdi)\t# clear AVX512F, ~(1\u003c\u003c16)\n+\t\t\t\t\t# note that we don't touch other AVX512\n+\t\t\t\t\t# extensions, because they can be used\n+\t\t\t\t\t# with YMM (without opmasking though)\n \tand\t\u005c$6,%eax\t\t# isolate XMM and YMM state support\n \tcmp\t\u005c$6,%eax\n \tje\t.Ldone\n .Lclear_avx:\n \tmov\t\u005c$0xefffe7ff,%eax\t# ~(1\u003c\u003c28|1\u003c\u003c12|1\u003c\u003c11)\n \tand\t%eax,%r9d\t\t# clear AVX, FMA and AMD XOP bits\n-\tandl\t\u005c$0xffffffdf,8(%rdi)\t# cleax AVX2, ~(1\u003c\u003c5)\n+\tmov\t\u005c$0x3fdeffdf,%eax\t# ~(1\u003c\u003c31|1\u003c\u003c30|1\u003c\u003c21|1\u003c\u003c16|1\u003c\u003c5)\n+\tand\t%eax,8(%rdi)\t\t# cleax AVX2 and AVX512* bits\n .Ldone:\n \tshl\t\u005c$32,%r9\n \tmov\t%r10d,%eax\n","s":{"c":1752735387,"u": 26507}} ],"g": 27872,"chitpc": 0,"ehitpc": 0,"indexed":0 , "ab": 0, "si": 0, "db":0, "di":0, "sat":0, "lfc": "0000"}