{"schema":"libjg2-1", "vpath":"/git/", "avatar":"/git/avatar/", "alang":"", "gen_ut":1752651711, "reponame":"openssl", "desc":"OpenSSL", "owner": { "name": "Andy Green", "email": "andy@warmcat.com", "md5": "c50933ca2aa61e0fe2c43d46bb6b59cb" },"url":"https://warmcat.com/repo/openssl", "f":3, "items": [ {"schema":"libjg2-1", "cid":"59fbb9e9b570936d9df867e1c594bcbf", "commit": {"type":"commit", "time": 1488467994, "time_ofs": 60, "oid_tree": { "oid": "8b63e44be3e2377adc9879f449043a1ddd7bfa8f", "alias": []}, "oid":{ "oid": "eac54143fd33f5f5140f3a6a55008a1453a8c369", "alias": []}, "msg": "bn/asm: clean up unused PA-RISC modules.", "sig_commit": { "git_time": { "time": 1488467994, "offset": 60 }, "name": "Andy Polyakov", "email": "appro@openssl.org", "md5": "50bd64fa2a792cbbf679fa16213a3b2a" }, "sig_author": { "git_time": { "time": 1488320736, "offset": 60 }, "name": "Andy Polyakov", "email": "appro@openssl.org", "md5": "50bd64fa2a792cbbf679fa16213a3b2a" }}, "body": "bn/asm: clean up unused PA-RISC modules.\n\nReviewed-by: Rich Salz \u003crsalz@openssl.org\u003e\n" , "diff": "diff --git a/crypto/bn/asm/pa-risc2.s b/crypto/bn/asm/pa-risc2.s\ndeleted file mode 100644\nindex 413eac7..0000000\n--- a/crypto/bn/asm/pa-risc2.s\n+++ /dev/null\n@@ -1,1624 +0,0 @@\n-; Copyright 1998-2016 The OpenSSL Project Authors. All Rights Reserved.\n-;\n-; Licensed under the OpenSSL license (the \u0022License\u0022). You may not use\n-; this file except in compliance with the License. You can obtain a copy\n-; in the file LICENSE in the source distribution or at\n-; https://www.openssl.org/source/license.html\n-;\n-; PA-RISC 2.0 implementation of bn_asm code, based on the\n-; 64-bit version of the code. This code is effectively the\n-; same as the 64-bit version except the register model is\n-; slightly different given all values must be 32-bit between\n-; function calls. Thus the 64-bit return values are returned\n-; in %ret0 and %ret1 vs just %ret0 as is done in 64-bit\n-;\n-;\n-; This code is approximately 2x faster than the C version\n-; for RSA/DSA.\n-;\n-; See http://devresource.hp.com/ for more details on the PA-RISC\n-; architecture. Also see the book \u0022PA-RISC 2.0 Architecture\u0022\n-; by Gerry Kane for information on the instruction set architecture.\n-;\n-; Code written by Chris Ruemmler (with some help from the HP C\n-; compiler).\n-;\n-; The code compiles with HP's assembler\n-;\n-\n-\t.level\t2.0N\n-\t.space\t$TEXT$\n-\t.subspa\t$CODE$,QUAD\u003d0,ALIGN\u003d8,ACCESS\u003d0x2c,CODE_ONLY\n-\n-;\n-; Global Register definitions used for the routines.\n-;\n-; Some information about HP's runtime architecture for 32-bits.\n-;\n-; \u0022Caller save\u0022 means the calling function must save the register\n-; if it wants the register to be preserved.\n-; \u0022Callee save\u0022 means if a function uses the register, it must save\n-; the value before using it.\n-;\n-; For the floating point registers \n-;\n-; \u0022caller save\u0022 registers: fr4-fr11, fr22-fr31\n-; \u0022callee save\u0022 registers: fr12-fr21\n-; \u0022special\u0022 registers: fr0-fr3 (status and exception registers)\n-;\n-; For the integer registers\n-; value zero : r0\n-; \u0022caller save\u0022 registers: r1,r19-r26\n-; \u0022callee save\u0022 registers: r3-r18\n-; return register : r2 (rp)\n-; return values ; r28,r29 (ret0,ret1)\n-; Stack pointer ; r30 (sp) \n-; millicode return ptr ; r31 (also a caller save register)\n-\n-\n-;\n-; Arguments to the routines\n-;\n-r_ptr .reg %r26\n-a_ptr .reg %r25\n-b_ptr .reg %r24\n-num .reg %r24\n-n .reg %r23\n-\n-;\n-; Note that the \u0022w\u0022 argument for bn_mul_add_words and bn_mul_words\n-; is passed on the stack at a delta of -56 from the top of stack\n-; as the routine is entered.\n-;\n-\n-;\n-; Globals used in some routines\n-;\n-\n-top_overflow .reg %r23\n-high_mask .reg %r22 ; value 0xffffffff80000000L\n-\n-\n-;------------------------------------------------------------------------------\n-;\n-; bn_mul_add_words\n-;\n-;BN_ULONG bn_mul_add_words(BN_ULONG *r_ptr, BN_ULONG *a_ptr, \n-;\t\t\t\t\t\t\t\tint num, BN_ULONG w)\n-;\n-; arg0 \u003d r_ptr\n-; arg1 \u003d a_ptr\n-; arg3 \u003d num\n-; -56(sp) \u003d w\n-;\n-; Local register definitions\n-;\n-\n-fm1 .reg %fr22\n-fm .reg %fr23\n-ht_temp .reg %fr24\n-ht_temp_1 .reg %fr25\n-lt_temp .reg %fr26\n-lt_temp_1 .reg %fr27\n-fm1_1 .reg %fr28\n-fm_1 .reg %fr29\n-\n-fw_h .reg %fr7L\n-fw_l .reg %fr7R\n-fw .reg %fr7\n-\n-fht_0 .reg %fr8L\n-flt_0 .reg %fr8R\n-t_float_0 .reg %fr8\n-\n-fht_1 .reg %fr9L\n-flt_1 .reg %fr9R\n-t_float_1 .reg %fr9\n-\n-tmp_0 .reg %r31\n-tmp_1 .reg %r21\n-m_0 .reg %r20 \n-m_1 .reg %r19 \n-ht_0 .reg %r1 \n-ht_1 .reg %r3\n-lt_0 .reg %r4\n-lt_1 .reg %r5\n-m1_0 .reg %r6 \n-m1_1 .reg %r7 \n-rp_val .reg %r8\n-rp_val_1 .reg %r9\n-\n-bn_mul_add_words\n-\t.export\tbn_mul_add_words,entry,NO_RELOCATION,LONG_RETURN\n-\t.proc\n-\t.callinfo frame\u003d128\n- .entry\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3 \n- STD %r4,8(%sp) ; save r4 \n-\tNOP ; Needed to make the loop 16-byte aligned\n-\tNOP ; needed to make the loop 16-byte aligned\n-\n- STD %r5,16(%sp) ; save r5 \n-\tNOP\n- STD %r6,24(%sp) ; save r6 \n- STD %r7,32(%sp) ; save r7 \n-\n- STD %r8,40(%sp) ; save r8 \n- STD %r9,48(%sp) ; save r9 \n- COPY %r0,%ret1 ; return 0 by default\n- DEPDI,Z 1,31,1,top_overflow ; top_overflow \u003d 1 \u003c\u003c 32 \n-\n- CMPIB,\u003e\u003d 0,num,bn_mul_add_words_exit ; if (num \u003c\u003d 0) then exit\n-\tLDO 128(%sp),%sp ; bump stack\n-\n-\t;\n-\t; The loop is unrolled twice, so if there is only 1 number\n- ; then go straight to the cleanup code.\n-\t;\n-\tCMPIB,\u003d 1,num,bn_mul_add_words_single_top\n-\tFLDD -184(%sp),fw ; (-56-128) load up w into fw (fw_h/fw_l)\n-\n-\t;\n-\t; This loop is unrolled 2 times (64-byte aligned as well)\n-\t;\n-\t; PA-RISC 2.0 chips have two fully pipelined multipliers, thus\n- ; two 32-bit mutiplies can be issued per cycle.\n- ; \n-bn_mul_add_words_unroll2\n-\n- FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n- FLDD 8(a_ptr),t_float_1 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n- LDD 0(r_ptr),rp_val ; rp[0]\n- LDD 8(r_ptr),rp_val_1 ; rp[1]\n-\n- XMPYU fht_0,fw_l,fm1 ; m1[0] \u003d fht_0*fw_l\n- XMPYU fht_1,fw_l,fm1_1 ; m1[1] \u003d fht_1*fw_l\n- FSTD fm1,-16(%sp) ; -16(sp) \u003d m1[0]\n- FSTD fm1_1,-48(%sp) ; -48(sp) \u003d m1[1]\n-\n- XMPYU flt_0,fw_h,fm ; m[0] \u003d flt_0*fw_h\n- XMPYU flt_1,fw_h,fm_1 ; m[1] \u003d flt_1*fw_h\n- FSTD fm,-8(%sp) ; -8(sp) \u003d m[0]\n- FSTD fm_1,-40(%sp) ; -40(sp) \u003d m[1]\n-\n- XMPYU fht_0,fw_h,ht_temp ; ht_temp \u003d fht_0*fw_h\n- XMPYU fht_1,fw_h,ht_temp_1 ; ht_temp_1 \u003d fht_1*fw_h\n- FSTD ht_temp,-24(%sp) ; -24(sp) \u003d ht_temp\n- FSTD ht_temp_1,-56(%sp) ; -56(sp) \u003d ht_temp_1\n-\n- XMPYU flt_0,fw_l,lt_temp ; lt_temp \u003d lt*fw_l\n- XMPYU flt_1,fw_l,lt_temp_1 ; lt_temp \u003d lt*fw_l\n- FSTD lt_temp,-32(%sp) ; -32(sp) \u003d lt_temp \n- FSTD lt_temp_1,-64(%sp) ; -64(sp) \u003d lt_temp_1 \n-\n- LDD -8(%sp),m_0 ; m[0] \n- LDD -40(%sp),m_1 ; m[1]\n- LDD -16(%sp),m1_0 ; m1[0]\n- LDD -48(%sp),m1_1 ; m1[1]\n-\n- LDD -24(%sp),ht_0 ; ht[0]\n- LDD -56(%sp),ht_1 ; ht[1]\n- ADD,L m1_0,m_0,tmp_0 ; tmp_0 \u003d m[0] + m1[0]; \n- ADD,L m1_1,m_1,tmp_1 ; tmp_1 \u003d m[1] + m1[1]; \n-\n- LDD -32(%sp),lt_0 \n- LDD -64(%sp),lt_1 \n- CMPCLR,*\u003e\u003e\u003d tmp_0,m1_0, %r0 ; if (m[0] \u003c m1[0])\n- ADD,L ht_0,top_overflow,ht_0 ; ht[0] +\u003d (1\u003c\u003c32)\n-\n- CMPCLR,*\u003e\u003e\u003d tmp_1,m1_1,%r0 ; if (m[1] \u003c m1[1])\n- ADD,L ht_1,top_overflow,ht_1 ; ht[1] +\u003d (1\u003c\u003c32)\n- EXTRD,U tmp_0,31,32,m_0 ; m[0]\u003e\u003e32 \n- DEPD,Z tmp_0,31,32,m1_0 ; m1[0] \u003d m[0]\u003c\u003c32 \n-\n- EXTRD,U tmp_1,31,32,m_1 ; m[1]\u003e\u003e32 \n- DEPD,Z tmp_1,31,32,m1_1 ; m1[1] \u003d m[1]\u003c\u003c32 \n- ADD,L ht_0,m_0,ht_0 ; ht[0]+\u003d (m[0]\u003e\u003e32)\n- ADD,L ht_1,m_1,ht_1 ; ht[1]+\u003d (m[1]\u003e\u003e32)\n-\n- ADD lt_0,m1_0,lt_0 ; lt[0] \u003d lt[0]+m1[0];\n-\tADD,DC ht_0,%r0,ht_0 ; ht[0]++\n- ADD lt_1,m1_1,lt_1 ; lt[1] \u003d lt[1]+m1[1];\n- ADD,DC ht_1,%r0,ht_1 ; ht[1]++\n-\n- ADD %ret1,lt_0,lt_0 ; lt[0] \u003d lt[0] + c;\n-\tADD,DC ht_0,%r0,ht_0 ; ht[0]++\n- ADD lt_0,rp_val,lt_0 ; lt[0] \u003d lt[0]+rp[0]\n- ADD,DC ht_0,%r0,ht_0 ; ht[0]++\n-\n-\tLDO -2(num),num ; num \u003d num - 2;\n- ADD ht_0,lt_1,lt_1 ; lt[1] \u003d lt[1] + ht_0 (c);\n- ADD,DC ht_1,%r0,ht_1 ; ht[1]++\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt[0]\n-\n- ADD lt_1,rp_val_1,lt_1 ; lt[1] \u003d lt[1]+rp[1]\n- ADD,DC ht_1,%r0,%ret1 ; ht[1]++\n- LDO 16(a_ptr),a_ptr ; a_ptr +\u003d 2\n-\n- STD lt_1,8(r_ptr) ; rp[1] \u003d lt[1]\n-\tCMPIB,\u003c\u003d 2,num,bn_mul_add_words_unroll2 ; go again if more to do\n- LDO 16(r_ptr),r_ptr ; r_ptr +\u003d 2\n-\n- CMPIB,\u003d,N 0,num,bn_mul_add_words_exit ; are we done, or cleanup last one\n-\n-\t;\n-\t; Top of loop aligned on 64-byte boundary\n-\t;\n-bn_mul_add_words_single_top\n- FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n- LDD 0(r_ptr),rp_val ; rp[0]\n- LDO 8(a_ptr),a_ptr ; a_ptr++\n- XMPYU fht_0,fw_l,fm1 ; m1 \u003d ht*fw_l\n- FSTD fm1,-16(%sp) ; -16(sp) \u003d m1\n- XMPYU flt_0,fw_h,fm ; m \u003d lt*fw_h\n- FSTD fm,-8(%sp) ; -8(sp) \u003d m\n- XMPYU fht_0,fw_h,ht_temp ; ht_temp \u003d ht*fw_h\n- FSTD ht_temp,-24(%sp) ; -24(sp) \u003d ht\n- XMPYU flt_0,fw_l,lt_temp ; lt_temp \u003d lt*fw_l\n- FSTD lt_temp,-32(%sp) ; -32(sp) \u003d lt \n-\n- LDD -8(%sp),m_0 \n- LDD -16(%sp),m1_0 ; m1 \u003d temp1 \n- ADD,L m_0,m1_0,tmp_0 ; tmp_0 \u003d m + m1; \n- LDD -24(%sp),ht_0 \n- LDD -32(%sp),lt_0 \n-\n- CMPCLR,*\u003e\u003e\u003d tmp_0,m1_0,%r0 ; if (m \u003c m1)\n- ADD,L ht_0,top_overflow,ht_0 ; ht +\u003d (1\u003c\u003c32)\n-\n- EXTRD,U tmp_0,31,32,m_0 ; m\u003e\u003e32 \n- DEPD,Z tmp_0,31,32,m1_0 ; m1 \u003d m\u003c\u003c32 \n-\n- ADD,L ht_0,m_0,ht_0 ; ht+\u003d (m\u003e\u003e32)\n- ADD lt_0,m1_0,tmp_0 ; tmp_0 \u003d lt+m1;\n- ADD,DC ht_0,%r0,ht_0 ; ht++\n- ADD %ret1,tmp_0,lt_0 ; lt \u003d lt + c;\n- ADD,DC ht_0,%r0,ht_0 ; ht++\n- ADD lt_0,rp_val,lt_0 ; lt \u003d lt+rp[0]\n- ADD,DC ht_0,%r0,%ret1 ; ht++\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt\n-\n-bn_mul_add_words_exit\n- .EXIT\n-\t\n- EXTRD,U %ret1,31,32,%ret0 ; for 32-bit, return in ret0/ret1\n- LDD -80(%sp),%r9 ; restore r9 \n- LDD -88(%sp),%r8 ; restore r8 \n- LDD -96(%sp),%r7 ; restore r7 \n- LDD -104(%sp),%r6 ; restore r6 \n- LDD -112(%sp),%r5 ; restore r5 \n- LDD -120(%sp),%r4 ; restore r4 \n- BVE (%rp)\n- LDD,MB -128(%sp),%r3 ; restore r3\n-\t.PROCEND\t;in\u003d23,24,25,26,29;out\u003d28;\n-\n-;----------------------------------------------------------------------------\n-;\n-;BN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)\n-;\n-; arg0 \u003d rp\n-; arg1 \u003d ap\n-; arg3 \u003d num\n-; w on stack at -56(sp)\n-\n-bn_mul_words\n-\t.proc\n-\t.callinfo frame\u003d128\n- .entry\n-\t.EXPORT\tbn_mul_words,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3 \n- STD %r4,8(%sp) ; save r4 \n-\tNOP\n- STD %r5,16(%sp) ; save r5 \n-\n- STD %r6,24(%sp) ; save r6 \n- STD %r7,32(%sp) ; save r7 \n- COPY %r0,%ret1 ; return 0 by default\n- DEPDI,Z 1,31,1,top_overflow ; top_overflow \u003d 1 \u003c\u003c 32 \n-\n- CMPIB,\u003e\u003d 0,num,bn_mul_words_exit\n-\tLDO 128(%sp),%sp ; bump stack\n-\n-\t;\n-\t; See if only 1 word to do, thus just do cleanup\n-\t;\n-\tCMPIB,\u003d 1,num,bn_mul_words_single_top\n-\tFLDD -184(%sp),fw ; (-56-128) load up w into fw (fw_h/fw_l)\n-\n-\t;\n-\t; This loop is unrolled 2 times (64-byte aligned as well)\n-\t;\n-\t; PA-RISC 2.0 chips have two fully pipelined multipliers, thus\n- ; two 32-bit mutiplies can be issued per cycle.\n- ; \n-bn_mul_words_unroll2\n-\n- FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n- FLDD 8(a_ptr),t_float_1 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n- XMPYU fht_0,fw_l,fm1 ; m1[0] \u003d fht_0*fw_l\n- XMPYU fht_1,fw_l,fm1_1 ; m1[1] \u003d ht*fw_l\n-\n- FSTD fm1,-16(%sp) ; -16(sp) \u003d m1\n- FSTD fm1_1,-48(%sp) ; -48(sp) \u003d m1\n- XMPYU flt_0,fw_h,fm ; m \u003d lt*fw_h\n- XMPYU flt_1,fw_h,fm_1 ; m \u003d lt*fw_h\n-\n- FSTD fm,-8(%sp) ; -8(sp) \u003d m\n- FSTD fm_1,-40(%sp) ; -40(sp) \u003d m\n- XMPYU fht_0,fw_h,ht_temp ; ht_temp \u003d fht_0*fw_h\n- XMPYU fht_1,fw_h,ht_temp_1 ; ht_temp \u003d ht*fw_h\n-\n- FSTD ht_temp,-24(%sp) ; -24(sp) \u003d ht\n- FSTD ht_temp_1,-56(%sp) ; -56(sp) \u003d ht\n- XMPYU flt_0,fw_l,lt_temp ; lt_temp \u003d lt*fw_l\n- XMPYU flt_1,fw_l,lt_temp_1 ; lt_temp \u003d lt*fw_l\n-\n- FSTD lt_temp,-32(%sp) ; -32(sp) \u003d lt \n- FSTD lt_temp_1,-64(%sp) ; -64(sp) \u003d lt \n- LDD -8(%sp),m_0 \n- LDD -40(%sp),m_1 \n-\n- LDD -16(%sp),m1_0 \n- LDD -48(%sp),m1_1 \n- LDD -24(%sp),ht_0 \n- LDD -56(%sp),ht_1 \n-\n- ADD,L m1_0,m_0,tmp_0 ; tmp_0 \u003d m + m1; \n- ADD,L m1_1,m_1,tmp_1 ; tmp_1 \u003d m + m1; \n- LDD -32(%sp),lt_0 \n- LDD -64(%sp),lt_1 \n-\n- CMPCLR,*\u003e\u003e\u003d tmp_0,m1_0, %r0 ; if (m \u003c m1)\n- ADD,L ht_0,top_overflow,ht_0 ; ht +\u003d (1\u003c\u003c32)\n- CMPCLR,*\u003e\u003e\u003d tmp_1,m1_1,%r0 ; if (m \u003c m1)\n- ADD,L ht_1,top_overflow,ht_1 ; ht +\u003d (1\u003c\u003c32)\n-\n- EXTRD,U tmp_0,31,32,m_0 ; m\u003e\u003e32 \n- DEPD,Z tmp_0,31,32,m1_0 ; m1 \u003d m\u003c\u003c32 \n- EXTRD,U tmp_1,31,32,m_1 ; m\u003e\u003e32 \n- DEPD,Z tmp_1,31,32,m1_1 ; m1 \u003d m\u003c\u003c32 \n-\n- ADD,L ht_0,m_0,ht_0 ; ht+\u003d (m\u003e\u003e32)\n- ADD,L ht_1,m_1,ht_1 ; ht+\u003d (m\u003e\u003e32)\n- ADD lt_0,m1_0,lt_0 ; lt \u003d lt+m1;\n-\tADD,DC ht_0,%r0,ht_0 ; ht++\n-\n- ADD lt_1,m1_1,lt_1 ; lt \u003d lt+m1;\n- ADD,DC ht_1,%r0,ht_1 ; ht++\n- ADD %ret1,lt_0,lt_0 ; lt \u003d lt + c (ret1);\n-\tADD,DC ht_0,%r0,ht_0 ; ht++\n-\n- ADD ht_0,lt_1,lt_1 ; lt \u003d lt + c (ht_0)\n- ADD,DC ht_1,%r0,ht_1 ; ht++\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt\n- STD lt_1,8(r_ptr) ; rp[1] \u003d lt\n-\n-\tCOPY ht_1,%ret1 ; carry \u003d ht\n-\tLDO -2(num),num ; num \u003d num - 2;\n- LDO 16(a_ptr),a_ptr ; ap +\u003d 2\n-\tCMPIB,\u003c\u003d 2,num,bn_mul_words_unroll2\n- LDO 16(r_ptr),r_ptr ; rp++\n-\n- CMPIB,\u003d,N 0,num,bn_mul_words_exit ; are we done?\n-\n-\t;\n-\t; Top of loop aligned on 64-byte boundary\n-\t;\n-bn_mul_words_single_top\n- FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n-\n- XMPYU fht_0,fw_l,fm1 ; m1 \u003d ht*fw_l\n- FSTD fm1,-16(%sp) ; -16(sp) \u003d m1\n- XMPYU flt_0,fw_h,fm ; m \u003d lt*fw_h\n- FSTD fm,-8(%sp) ; -8(sp) \u003d m\n- XMPYU fht_0,fw_h,ht_temp ; ht_temp \u003d ht*fw_h\n- FSTD ht_temp,-24(%sp) ; -24(sp) \u003d ht\n- XMPYU flt_0,fw_l,lt_temp ; lt_temp \u003d lt*fw_l\n- FSTD lt_temp,-32(%sp) ; -32(sp) \u003d lt \n-\n- LDD -8(%sp),m_0 \n- LDD -16(%sp),m1_0 \n- ADD,L m_0,m1_0,tmp_0 ; tmp_0 \u003d m + m1; \n- LDD -24(%sp),ht_0 \n- LDD -32(%sp),lt_0 \n-\n- CMPCLR,*\u003e\u003e\u003d tmp_0,m1_0,%r0 ; if (m \u003c m1)\n- ADD,L ht_0,top_overflow,ht_0 ; ht +\u003d (1\u003c\u003c32)\n-\n- EXTRD,U tmp_0,31,32,m_0 ; m\u003e\u003e32 \n- DEPD,Z tmp_0,31,32,m1_0 ; m1 \u003d m\u003c\u003c32 \n-\n- ADD,L ht_0,m_0,ht_0 ; ht+\u003d (m\u003e\u003e32)\n- ADD lt_0,m1_0,lt_0 ; lt\u003d lt+m1;\n- ADD,DC ht_0,%r0,ht_0 ; ht++\n-\n- ADD %ret1,lt_0,lt_0 ; lt \u003d lt + c;\n- ADD,DC ht_0,%r0,ht_0 ; ht++\n-\n- COPY ht_0,%ret1 ; copy carry\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt\n-\n-bn_mul_words_exit\n- .EXIT\n- EXTRD,U %ret1,31,32,%ret0 ; for 32-bit, return in ret0/ret1\n- LDD -96(%sp),%r7 ; restore r7 \n- LDD -104(%sp),%r6 ; restore r6 \n- LDD -112(%sp),%r5 ; restore r5 \n- LDD -120(%sp),%r4 ; restore r4 \n- BVE (%rp)\n- LDD,MB -128(%sp),%r3 ; restore r3\n-\t.PROCEND\t\n-\n-;----------------------------------------------------------------------------\n-;\n-;void bn_sqr_words(BN_ULONG *rp, BN_ULONG *ap, int num)\n-;\n-; arg0 \u003d rp\n-; arg1 \u003d ap\n-; arg2 \u003d num\n-;\n-\n-bn_sqr_words\n-\t.proc\n-\t.callinfo FRAME\u003d128,ENTRY_GR\u003d%r3,ARGS_SAVED,ORDERING_AWARE\n-\t.EXPORT\tbn_sqr_words,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .entry\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3 \n- STD %r4,8(%sp) ; save r4 \n-\tNOP\n- STD %r5,16(%sp) ; save r5 \n-\n- CMPIB,\u003e\u003d 0,num,bn_sqr_words_exit\n-\tLDO 128(%sp),%sp ; bump stack\n-\n-\t;\n-\t; If only 1, the goto straight to cleanup\n-\t;\n-\tCMPIB,\u003d 1,num,bn_sqr_words_single_top\n- DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L\n-\n-\t;\n-\t; This loop is unrolled 2 times (64-byte aligned as well)\n-\t;\n-\n-bn_sqr_words_unroll2\n- FLDD 0(a_ptr),t_float_0 ; a[0]\n- FLDD 8(a_ptr),t_float_1 ; a[1]\n- XMPYU fht_0,flt_0,fm ; m[0]\n- XMPYU fht_1,flt_1,fm_1 ; m[1]\n-\n- FSTD fm,-24(%sp) ; store m[0]\n- FSTD fm_1,-56(%sp) ; store m[1]\n- XMPYU flt_0,flt_0,lt_temp ; lt[0]\n- XMPYU flt_1,flt_1,lt_temp_1 ; lt[1]\n-\n- FSTD lt_temp,-16(%sp) ; store lt[0]\n- FSTD lt_temp_1,-48(%sp) ; store lt[1]\n- XMPYU fht_0,fht_0,ht_temp ; ht[0]\n- XMPYU fht_1,fht_1,ht_temp_1 ; ht[1]\n-\n- FSTD ht_temp,-8(%sp) ; store ht[0]\n- FSTD ht_temp_1,-40(%sp) ; store ht[1]\n- LDD -24(%sp),m_0 \n- LDD -56(%sp),m_1 \n-\n- AND m_0,high_mask,tmp_0 ; m[0] \u0026 Mask\n- AND m_1,high_mask,tmp_1 ; m[1] \u0026 Mask\n- DEPD,Z m_0,30,31,m_0 ; m[0] \u003c\u003c 32+1\n- DEPD,Z m_1,30,31,m_1 ; m[1] \u003c\u003c 32+1\n-\n- LDD -16(%sp),lt_0 \n- LDD -48(%sp),lt_1 \n- EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 \u003d m[0]\u0026Mask \u003e\u003e 32-1\n- EXTRD,U tmp_1,32,33,tmp_1 ; tmp_1 \u003d m[1]\u0026Mask \u003e\u003e 32-1\n-\n- LDD -8(%sp),ht_0 \n- LDD -40(%sp),ht_1 \n- ADD,L ht_0,tmp_0,ht_0 ; ht[0] +\u003d tmp_0\n- ADD,L ht_1,tmp_1,ht_1 ; ht[1] +\u003d tmp_1\n-\n- ADD lt_0,m_0,lt_0 ; lt \u003d lt+m\n- ADD,DC ht_0,%r0,ht_0 ; ht[0]++\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt[0]\n- STD ht_0,8(r_ptr) ; rp[1] \u003d ht[1]\n-\n- ADD lt_1,m_1,lt_1 ; lt \u003d lt+m\n- ADD,DC ht_1,%r0,ht_1 ; ht[1]++\n- STD lt_1,16(r_ptr) ; rp[2] \u003d lt[1]\n- STD ht_1,24(r_ptr) ; rp[3] \u003d ht[1]\n-\n-\tLDO -2(num),num ; num \u003d num - 2;\n- LDO 16(a_ptr),a_ptr ; ap +\u003d 2\n-\tCMPIB,\u003c\u003d 2,num,bn_sqr_words_unroll2\n- LDO 32(r_ptr),r_ptr ; rp +\u003d 4\n-\n- CMPIB,\u003d,N 0,num,bn_sqr_words_exit ; are we done?\n-\n-\t;\n-\t; Top of loop aligned on 64-byte boundary\n-\t;\n-bn_sqr_words_single_top\n- FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n-\n- XMPYU fht_0,flt_0,fm ; m\n- FSTD fm,-24(%sp) ; store m\n-\n- XMPYU flt_0,flt_0,lt_temp ; lt\n- FSTD lt_temp,-16(%sp) ; store lt\n-\n- XMPYU fht_0,fht_0,ht_temp ; ht\n- FSTD ht_temp,-8(%sp) ; store ht\n-\n- LDD -24(%sp),m_0 ; load m\n- AND m_0,high_mask,tmp_0 ; m \u0026 Mask\n- DEPD,Z m_0,30,31,m_0 ; m \u003c\u003c 32+1\n- LDD -16(%sp),lt_0 ; lt\n-\n- LDD -8(%sp),ht_0 ; ht\n- EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 \u003d m\u0026Mask \u003e\u003e 32-1\n- ADD m_0,lt_0,lt_0 ; lt \u003d lt+m\n- ADD,L ht_0,tmp_0,ht_0 ; ht +\u003d tmp_0\n- ADD,DC ht_0,%r0,ht_0 ; ht++\n-\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt\n- STD ht_0,8(r_ptr) ; rp[1] \u003d ht\n-\n-bn_sqr_words_exit\n- .EXIT\n- LDD -112(%sp),%r5 ; restore r5 \n- LDD -120(%sp),%r4 ; restore r4 \n- BVE (%rp)\n- LDD,MB -128(%sp),%r3 \n-\t.PROCEND\t;in\u003d23,24,25,26,29;out\u003d28;\n-\n-\n-;----------------------------------------------------------------------------\n-;\n-;BN_ULONG bn_add_words(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b, int n)\n-;\n-; arg0 \u003d rp \n-; arg1 \u003d ap\n-; arg2 \u003d bp \n-; arg3 \u003d n\n-\n-t .reg %r22\n-b .reg %r21\n-l .reg %r20\n-\n-bn_add_words\n-\t.proc\n- .entry\n-\t.callinfo\n-\t.EXPORT\tbn_add_words,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n-\t.align 64\n-\n- CMPIB,\u003e\u003d 0,n,bn_add_words_exit\n- COPY %r0,%ret1 ; return 0 by default\n-\n-\t;\n-\t; If 2 or more numbers do the loop\n-\t;\n-\tCMPIB,\u003d 1,n,bn_add_words_single_top\n-\tNOP\n-\n-\t;\n-\t; This loop is unrolled 2 times (64-byte aligned as well)\n-\t;\n-bn_add_words_unroll2\n-\tLDD 0(a_ptr),t\n-\tLDD 0(b_ptr),b\n-\tADD t,%ret1,t ; t \u003d t+c;\n-\tADD,DC %r0,%r0,%ret1 ; set c to carry\n-\tADD t,b,l ; l \u003d t + b[0]\n-\tADD,DC %ret1,%r0,%ret1 ; c+\u003d carry\n-\tSTD l,0(r_ptr)\n-\n-\tLDD 8(a_ptr),t\n-\tLDD 8(b_ptr),b\n-\tADD t,%ret1,t ; t \u003d t+c;\n-\tADD,DC %r0,%r0,%ret1 ; set c to carry\n-\tADD t,b,l ; l \u003d t + b[0]\n-\tADD,DC %ret1,%r0,%ret1 ; c+\u003d carry\n-\tSTD l,8(r_ptr)\n-\n-\tLDO -2(n),n\n-\tLDO 16(a_ptr),a_ptr\n-\tLDO 16(b_ptr),b_ptr\n-\n-\tCMPIB,\u003c\u003d 2,n,bn_add_words_unroll2\n-\tLDO 16(r_ptr),r_ptr\n-\n- CMPIB,\u003d,N 0,n,bn_add_words_exit ; are we done?\n-\n-bn_add_words_single_top\n-\tLDD 0(a_ptr),t\n-\tLDD 0(b_ptr),b\n-\n-\tADD t,%ret1,t ; t \u003d t+c;\n-\tADD,DC %r0,%r0,%ret1 ; set c to carry (could use CMPCLR??)\n-\tADD t,b,l ; l \u003d t + b[0]\n-\tADD,DC %ret1,%r0,%ret1 ; c+\u003d carry\n-\tSTD l,0(r_ptr)\n-\n-bn_add_words_exit\n- .EXIT\n- BVE (%rp)\n- EXTRD,U %ret1,31,32,%ret0 ; for 32-bit, return in ret0/ret1\n-\t.PROCEND\t;in\u003d23,24,25,26,29;out\u003d28;\n-\n-;----------------------------------------------------------------------------\n-;\n-;BN_ULONG bn_sub_words(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b, int n)\n-;\n-; arg0 \u003d rp \n-; arg1 \u003d ap\n-; arg2 \u003d bp \n-; arg3 \u003d n\n-\n-t1 .reg %r22\n-t2 .reg %r21\n-sub_tmp1 .reg %r20\n-sub_tmp2 .reg %r19\n-\n-\n-bn_sub_words\n-\t.proc\n-\t.callinfo \n-\t.EXPORT\tbn_sub_words,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .entry\n-\t.align 64\n-\n- CMPIB,\u003e\u003d 0,n,bn_sub_words_exit\n- COPY %r0,%ret1 ; return 0 by default\n-\n-\t;\n-\t; If 2 or more numbers do the loop\n-\t;\n-\tCMPIB,\u003d 1,n,bn_sub_words_single_top\n-\tNOP\n-\n-\t;\n-\t; This loop is unrolled 2 times (64-byte aligned as well)\n-\t;\n-bn_sub_words_unroll2\n-\tLDD 0(a_ptr),t1\n-\tLDD 0(b_ptr),t2\n-\tSUB t1,t2,sub_tmp1 ; t3 \u003d t1-t2; \n-\tSUB sub_tmp1,%ret1,sub_tmp1 ; t3 \u003d t3- c; \n-\n-\tCMPCLR,*\u003e\u003e t1,t2,sub_tmp2 ; clear if t1 \u003e t2\n-\tLDO 1(%r0),sub_tmp2\n-\t\n-\tCMPCLR,*\u003d t1,t2,%r0\n-\tCOPY sub_tmp2,%ret1\n-\tSTD sub_tmp1,0(r_ptr)\n-\n-\tLDD 8(a_ptr),t1\n-\tLDD 8(b_ptr),t2\n-\tSUB t1,t2,sub_tmp1 ; t3 \u003d t1-t2; \n-\tSUB sub_tmp1,%ret1,sub_tmp1 ; t3 \u003d t3- c; \n-\tCMPCLR,*\u003e\u003e t1,t2,sub_tmp2 ; clear if t1 \u003e t2\n-\tLDO 1(%r0),sub_tmp2\n-\t\n-\tCMPCLR,*\u003d t1,t2,%r0\n-\tCOPY sub_tmp2,%ret1\n-\tSTD sub_tmp1,8(r_ptr)\n-\n-\tLDO -2(n),n\n-\tLDO 16(a_ptr),a_ptr\n-\tLDO 16(b_ptr),b_ptr\n-\n-\tCMPIB,\u003c\u003d 2,n,bn_sub_words_unroll2\n-\tLDO 16(r_ptr),r_ptr\n-\n- CMPIB,\u003d,N 0,n,bn_sub_words_exit ; are we done?\n-\n-bn_sub_words_single_top\n-\tLDD 0(a_ptr),t1\n-\tLDD 0(b_ptr),t2\n-\tSUB t1,t2,sub_tmp1 ; t3 \u003d t1-t2; \n-\tSUB sub_tmp1,%ret1,sub_tmp1 ; t3 \u003d t3- c; \n-\tCMPCLR,*\u003e\u003e t1,t2,sub_tmp2 ; clear if t1 \u003e t2\n-\tLDO 1(%r0),sub_tmp2\n-\t\n-\tCMPCLR,*\u003d t1,t2,%r0\n-\tCOPY sub_tmp2,%ret1\n-\n-\tSTD sub_tmp1,0(r_ptr)\n-\n-bn_sub_words_exit\n- .EXIT\n- BVE (%rp)\n- EXTRD,U %ret1,31,32,%ret0 ; for 32-bit, return in ret0/ret1\n-\t.PROCEND\t;in\u003d23,24,25,26,29;out\u003d28;\n-\n-;------------------------------------------------------------------------------\n-;\n-; unsigned long bn_div_words(unsigned long h, unsigned long l, unsigned long d)\n-;\n-; arg0 \u003d h\n-; arg1 \u003d l\n-; arg2 \u003d d\n-;\n-; This is mainly just output from the HP C compiler. \n-;\n-;------------------------------------------------------------------------------\n-bn_div_words\n-\t.PROC\n-\t.EXPORT\tbn_div_words,ENTRY,PRIV_LEV\u003d3,ARGW0\u003dGR,ARGW1\u003dGR,ARGW2\u003dGR,ARGW3\u003dGR,RTNVAL\u003dGR,LONG_RETURN\n-\t.IMPORT\tBN_num_bits_word,CODE\n-\t;--- not PIC\t.IMPORT\t__iob,DATA\n-\t;--- not PIC\t.IMPORT\tfprintf,CODE\n-\t.IMPORT\tabort,CODE\n-\t.IMPORT\t$$div2U,MILLICODE\n-\t.CALLINFO CALLER,FRAME\u003d144,ENTRY_GR\u003d%r9,SAVE_RP,ARGS_SAVED,ORDERING_AWARE\n- .ENTRY\n- STW %r2,-20(%r30) ;offset 0x8ec\n- STW,MA %r3,192(%r30) ;offset 0x8f0\n- STW %r4,-188(%r30) ;offset 0x8f4\n- DEPD %r5,31,32,%r6 ;offset 0x8f8\n- STD %r6,-184(%r30) ;offset 0x8fc\n- DEPD %r7,31,32,%r8 ;offset 0x900\n- STD %r8,-176(%r30) ;offset 0x904\n- STW %r9,-168(%r30) ;offset 0x908\n- LDD -248(%r30),%r3 ;offset 0x90c\n- COPY %r26,%r4 ;offset 0x910\n- COPY %r24,%r5 ;offset 0x914\n- DEPD %r25,31,32,%r4 ;offset 0x918\n- CMPB,*\u003c\u003e %r3,%r0,$0006000C ;offset 0x91c\n- DEPD %r23,31,32,%r5 ;offset 0x920\n- MOVIB,TR -1,%r29,$00060002 ;offset 0x924\n- EXTRD,U %r29,31,32,%r28 ;offset 0x928\n-$0006002A\n- LDO -1(%r29),%r29 ;offset 0x92c\n- SUB %r23,%r7,%r23 ;offset 0x930\n-$00060024\n- SUB %r4,%r31,%r25 ;offset 0x934\n- AND %r25,%r19,%r26 ;offset 0x938\n- CMPB,*\u003c\u003e,N %r0,%r26,$00060046 ;offset 0x93c\n- DEPD,Z %r25,31,32,%r20 ;offset 0x940\n- OR %r20,%r24,%r21 ;offset 0x944\n- CMPB,*\u003c\u003c,N %r21,%r23,$0006002A ;offset 0x948\n- SUB %r31,%r2,%r31 ;offset 0x94c\n-$00060046\n-$0006002E\n- DEPD,Z %r23,31,32,%r25 ;offset 0x950\n- EXTRD,U %r23,31,32,%r26 ;offset 0x954\n- AND %r25,%r19,%r24 ;offset 0x958\n- ADD,L %r31,%r26,%r31 ;offset 0x95c\n- CMPCLR,*\u003e\u003e\u003d %r5,%r24,%r0 ;offset 0x960\n- LDO 1(%r31),%r31 ;offset 0x964\n-$00060032\n- CMPB,*\u003c\u003c\u003d,N %r31,%r4,$00060036 ;offset 0x968\n- LDO -1(%r29),%r29 ;offset 0x96c\n- ADD,L %r4,%r3,%r4 ;offset 0x970\n-$00060036\n- ADDIB,\u003d,N -1,%r8,$D0 ;offset 0x974\n- SUB %r5,%r24,%r28 ;offset 0x978\n-$0006003A\n- SUB %r4,%r31,%r24 ;offset 0x97c\n- SHRPD %r24,%r28,32,%r4 ;offset 0x980\n- DEPD,Z %r29,31,32,%r9 ;offset 0x984\n- DEPD,Z %r28,31,32,%r5 ;offset 0x988\n-$0006001C\n- EXTRD,U %r4,31,32,%r31 ;offset 0x98c\n- CMPB,*\u003c\u003e,N %r31,%r2,$00060020 ;offset 0x990\n- MOVB,TR %r6,%r29,$D1 ;offset 0x994\n- STD %r29,-152(%r30) ;offset 0x998\n-$0006000C\n- EXTRD,U %r3,31,32,%r25 ;offset 0x99c\n- COPY %r3,%r26 ;offset 0x9a0\n- EXTRD,U %r3,31,32,%r9 ;offset 0x9a4\n- EXTRD,U %r4,31,32,%r8 ;offset 0x9a8\n- .CALL ARGW0\u003dGR,ARGW1\u003dGR,RTNVAL\u003dGR ;in\u003d25,26;out\u003d28;\n- B,L BN_num_bits_word,%r2 ;offset 0x9ac\n- EXTRD,U %r5,31,32,%r7 ;offset 0x9b0\n- LDI 64,%r20 ;offset 0x9b4\n- DEPD %r7,31,32,%r5 ;offset 0x9b8\n- DEPD %r8,31,32,%r4 ;offset 0x9bc\n- DEPD %r9,31,32,%r3 ;offset 0x9c0\n- CMPB,\u003d %r28,%r20,$00060012 ;offset 0x9c4\n- COPY %r28,%r24 ;offset 0x9c8\n- MTSARCM %r24 ;offset 0x9cc\n- DEPDI,Z -1,%sar,1,%r19 ;offset 0x9d0\n- CMPB,*\u003e\u003e,N %r4,%r19,$D2 ;offset 0x9d4\n-$00060012\n- SUBI 64,%r24,%r31 ;offset 0x9d8\n- CMPCLR,*\u003c\u003c %r4,%r3,%r0 ;offset 0x9dc\n- SUB %r4,%r3,%r4 ;offset 0x9e0\n-$00060016\n- CMPB,\u003d %r31,%r0,$0006001A ;offset 0x9e4\n- COPY %r0,%r9 ;offset 0x9e8\n- MTSARCM %r31 ;offset 0x9ec\n- DEPD,Z %r3,%sar,64,%r3 ;offset 0x9f0\n- SUBI 64,%r31,%r26 ;offset 0x9f4\n- MTSAR %r26 ;offset 0x9f8\n- SHRPD %r4,%r5,%sar,%r4 ;offset 0x9fc\n- MTSARCM %r31 ;offset 0xa00\n- DEPD,Z %r5,%sar,64,%r5 ;offset 0xa04\n-$0006001A\n- DEPDI,Z -1,31,32,%r19 ;offset 0xa08\n- AND %r3,%r19,%r29 ;offset 0xa0c\n- EXTRD,U %r29,31,32,%r2 ;offset 0xa10\n- DEPDI,Z -1,63,32,%r6 ;offset 0xa14\n- MOVIB,TR 2,%r8,$0006001C ;offset 0xa18\n- EXTRD,U %r3,63,32,%r7 ;offset 0xa1c\n-$D2\n- ;--- not PIC\tADDIL LR'__iob-$global$,%r27,%r1 ;offset 0xa20\n- ;--- not PIC\tLDIL LR'C$7,%r21 ;offset 0xa24\n- ;--- not PIC\tLDO RR'__iob-$global$+32(%r1),%r26 ;offset 0xa28\n- ;--- not PIC\t.CALL ARGW0\u003dGR,ARGW1\u003dGR,ARGW2\u003dGR,RTNVAL\u003dGR ;in\u003d24,25,26;out\u003d28;\n- ;--- not PIC\tB,L fprintf,%r2 ;offset 0xa2c\n- ;--- not PIC\tLDO RR'C$7(%r21),%r25 ;offset 0xa30\n- .CALL ;\n- B,L abort,%r2 ;offset 0xa34\n- NOP ;offset 0xa38\n- B $D3 ;offset 0xa3c\n- LDW -212(%r30),%r2 ;offset 0xa40\n-$00060020\n- COPY %r4,%r26 ;offset 0xa44\n- EXTRD,U %r4,31,32,%r25 ;offset 0xa48\n- COPY %r2,%r24 ;offset 0xa4c\n- .CALL ;in\u003d23,24,25,26;out\u003d20,21,22,28,29; (MILLICALL)\n- B,L $$div2U,%r31 ;offset 0xa50\n- EXTRD,U %r2,31,32,%r23 ;offset 0xa54\n- DEPD %r28,31,32,%r29 ;offset 0xa58\n-$00060022\n- STD %r29,-152(%r30) ;offset 0xa5c\n-$D1\n- AND %r5,%r19,%r24 ;offset 0xa60\n- EXTRD,U %r24,31,32,%r24 ;offset 0xa64\n- STW %r2,-160(%r30) ;offset 0xa68\n- STW %r7,-128(%r30) ;offset 0xa6c\n- FLDD -152(%r30),%fr4 ;offset 0xa70\n- FLDD -152(%r30),%fr7 ;offset 0xa74\n- FLDW -160(%r30),%fr8L ;offset 0xa78\n- FLDW -128(%r30),%fr5L ;offset 0xa7c\n- XMPYU %fr8L,%fr7L,%fr10 ;offset 0xa80\n- FSTD %fr10,-136(%r30) ;offset 0xa84\n- XMPYU %fr8L,%fr7R,%fr22 ;offset 0xa88\n- FSTD %fr22,-144(%r30) ;offset 0xa8c\n- XMPYU %fr5L,%fr4L,%fr11 ;offset 0xa90\n- XMPYU %fr5L,%fr4R,%fr23 ;offset 0xa94\n- FSTD %fr11,-112(%r30) ;offset 0xa98\n- FSTD %fr23,-120(%r30) ;offset 0xa9c\n- LDD -136(%r30),%r28 ;offset 0xaa0\n- DEPD,Z %r28,31,32,%r31 ;offset 0xaa4\n- LDD -144(%r30),%r20 ;offset 0xaa8\n- ADD,L %r20,%r31,%r31 ;offset 0xaac\n- LDD -112(%r30),%r22 ;offset 0xab0\n- DEPD,Z %r22,31,32,%r22 ;offset 0xab4\n- LDD -120(%r30),%r21 ;offset 0xab8\n- B $00060024 ;offset 0xabc\n- ADD,L %r21,%r22,%r23 ;offset 0xac0\n-$D0\n- OR %r9,%r29,%r29 ;offset 0xac4\n-$00060040\n- EXTRD,U %r29,31,32,%r28 ;offset 0xac8\n-$00060002\n-$L2\n- LDW -212(%r30),%r2 ;offset 0xacc\n-$D3\n- LDW -168(%r30),%r9 ;offset 0xad0\n- LDD -176(%r30),%r8 ;offset 0xad4\n- EXTRD,U %r8,31,32,%r7 ;offset 0xad8\n- LDD -184(%r30),%r6 ;offset 0xadc\n- EXTRD,U %r6,31,32,%r5 ;offset 0xae0\n- LDW -188(%r30),%r4 ;offset 0xae4\n- BVE (%r2) ;offset 0xae8\n- .EXIT\n- LDW,MB -192(%r30),%r3 ;offset 0xaec\n-\t.PROCEND\t;in\u003d23,25;out\u003d28,29;fpin\u003d105,107;\n-\n-\n-\n-\n-;----------------------------------------------------------------------------\n-;\n-; Registers to hold 64-bit values to manipulate. The \u0022L\u0022 part\n-; of the register corresponds to the upper 32-bits, while the \u0022R\u0022\n-; part corresponds to the lower 32-bits\n-; \n-; Note, that when using b6 and b7, the code must save these before\n-; using them because they are callee save registers \n-; \n-;\n-; Floating point registers to use to save values that\n-; are manipulated. These don't collide with ftemp1-6 and\n-; are all caller save registers\n-;\n-a0 .reg %fr22\n-a0L .reg %fr22L\n-a0R .reg %fr22R\n-\n-a1 .reg %fr23\n-a1L .reg %fr23L\n-a1R .reg %fr23R\n-\n-a2 .reg %fr24\n-a2L .reg %fr24L\n-a2R .reg %fr24R\n-\n-a3 .reg %fr25\n-a3L .reg %fr25L\n-a3R .reg %fr25R\n-\n-a4 .reg %fr26\n-a4L .reg %fr26L\n-a4R .reg %fr26R\n-\n-a5 .reg %fr27\n-a5L .reg %fr27L\n-a5R .reg %fr27R\n-\n-a6 .reg %fr28\n-a6L .reg %fr28L\n-a6R .reg %fr28R\n-\n-a7 .reg %fr29\n-a7L .reg %fr29L\n-a7R .reg %fr29R\n-\n-b0 .reg %fr30\n-b0L .reg %fr30L\n-b0R .reg %fr30R\n-\n-b1 .reg %fr31\n-b1L .reg %fr31L\n-b1R .reg %fr31R\n-\n-;\n-; Temporary floating point variables, these are all caller save\n-; registers\n-;\n-ftemp1 .reg %fr4\n-ftemp2 .reg %fr5\n-ftemp3 .reg %fr6\n-ftemp4 .reg %fr7\n-\n-;\n-; The B set of registers when used.\n-;\n-\n-b2 .reg %fr8\n-b2L .reg %fr8L\n-b2R .reg %fr8R\n-\n-b3 .reg %fr9\n-b3L .reg %fr9L\n-b3R .reg %fr9R\n-\n-b4 .reg %fr10\n-b4L .reg %fr10L\n-b4R .reg %fr10R\n-\n-b5 .reg %fr11\n-b5L .reg %fr11L\n-b5R .reg %fr11R\n-\n-b6 .reg %fr12\n-b6L .reg %fr12L\n-b6R .reg %fr12R\n-\n-b7 .reg %fr13\n-b7L .reg %fr13L\n-b7R .reg %fr13R\n-\n-c1 .reg %r21 ; only reg\n-temp1 .reg %r20 ; only reg\n-temp2 .reg %r19 ; only reg\n-temp3 .reg %r31 ; only reg\n-\n-m1 .reg %r28 \n-c2 .reg %r23 \n-high_one .reg %r1\n-ht .reg %r6\n-lt .reg %r5\n-m .reg %r4\n-c3 .reg %r3\n-\n-SQR_ADD_C .macro A0L,A0R,C1,C2,C3\n- XMPYU A0L,A0R,ftemp1 ; m\n- FSTD ftemp1,-24(%sp) ; store m\n-\n- XMPYU A0R,A0R,ftemp2 ; lt\n- FSTD ftemp2,-16(%sp) ; store lt\n-\n- XMPYU A0L,A0L,ftemp3 ; ht\n- FSTD ftemp3,-8(%sp) ; store ht\n-\n- LDD -24(%sp),m ; load m\n- AND m,high_mask,temp2 ; m \u0026 Mask\n- DEPD,Z m,30,31,temp3 ; m \u003c\u003c 32+1\n- LDD -16(%sp),lt ; lt\n-\n- LDD -8(%sp),ht ; ht\n- EXTRD,U temp2,32,33,temp1 ; temp1 \u003d m\u0026Mask \u003e\u003e 32-1\n- ADD temp3,lt,lt ; lt \u003d lt+m\n- ADD,L ht,temp1,ht ; ht +\u003d temp1\n- ADD,DC ht,%r0,ht ; ht++\n-\n- ADD C1,lt,C1 ; c1\u003dc1+lt\n- ADD,DC ht,%r0,ht ; ht++\n-\n- ADD C2,ht,C2 ; c2\u003dc2+ht\n- ADD,DC C3,%r0,C3 ; c3++\n-.endm\n-\n-SQR_ADD_C2 .macro A0L,A0R,A1L,A1R,C1,C2,C3\n- XMPYU A0L,A1R,ftemp1 ; m1 \u003d bl*ht\n- FSTD ftemp1,-16(%sp) ;\n- XMPYU A0R,A1L,ftemp2 ; m \u003d bh*lt\n- FSTD ftemp2,-8(%sp) ;\n- XMPYU A0R,A1R,ftemp3 ; lt \u003d bl*lt\n- FSTD ftemp3,-32(%sp)\n- XMPYU A0L,A1L,ftemp4 ; ht \u003d bh*ht\n- FSTD ftemp4,-24(%sp) ;\n-\n- LDD -8(%sp),m ; r21 \u003d m\n- LDD -16(%sp),m1 ; r19 \u003d m1\n- ADD,L m,m1,m ; m+m1\n-\n- DEPD,Z m,31,32,temp3 ; (m+m1\u003c\u003c32)\n- LDD -24(%sp),ht ; r24 \u003d ht\n-\n- CMPCLR,*\u003e\u003e\u003d m,m1,%r0 ; if (m \u003c m1)\n- ADD,L ht,high_one,ht ; ht+\u003dhigh_one\n-\n- EXTRD,U m,31,32,temp1 ; m \u003e\u003e 32\n- LDD -32(%sp),lt ; lt\n- ADD,L ht,temp1,ht ; ht+\u003d m\u003e\u003e32\n- ADD lt,temp3,lt ; lt \u003d lt+m1\n- ADD,DC ht,%r0,ht ; ht++\n-\n- ADD ht,ht,ht ; ht\u003dht+ht;\n- ADD,DC C3,%r0,C3 ; add in carry (c3++)\n-\n- ADD lt,lt,lt ; lt\u003dlt+lt;\n- ADD,DC ht,%r0,ht ; add in carry (ht++)\n-\n- ADD C1,lt,C1 ; c1\u003dc1+lt\n- ADD,DC,*NUV ht,%r0,ht ; add in carry (ht++)\n- LDO 1(C3),C3 ; bump c3 if overflow,nullify otherwise\n-\n- ADD C2,ht,C2 ; c2 \u003d c2 + ht\n- ADD,DC C3,%r0,C3 ; add in carry (c3++)\n-.endm\n-\n-;\n-;void bn_sqr_comba8(BN_ULONG *r, BN_ULONG *a)\n-; arg0 \u003d r_ptr\n-; arg1 \u003d a_ptr\n-;\n-\n-bn_sqr_comba8\n-\t.PROC\n-\t.CALLINFO FRAME\u003d128,ENTRY_GR\u003d%r3,ARGS_SAVED,ORDERING_AWARE\n-\t.EXPORT\tbn_sqr_comba8,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .ENTRY\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3\n- STD %r4,8(%sp) ; save r4\n- STD %r5,16(%sp) ; save r5\n- STD %r6,24(%sp) ; save r6\n-\n-\t;\n-\t; Zero out carries\n-\t;\n-\tCOPY %r0,c1\n-\tCOPY %r0,c2\n-\tCOPY %r0,c3\n-\n-\tLDO 128(%sp),%sp ; bump stack\n- DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L\n- DEPDI,Z 1,31,1,high_one ; Create Value 1 \u003c\u003c 32\n-\n-\t;\n-\t; Load up all of the values we are going to use\n-\t;\n- FLDD 0(a_ptr),a0 \n- FLDD 8(a_ptr),a1 \n- FLDD 16(a_ptr),a2 \n- FLDD 24(a_ptr),a3 \n- FLDD 32(a_ptr),a4 \n- FLDD 40(a_ptr),a5 \n- FLDD 48(a_ptr),a6 \n- FLDD 56(a_ptr),a7 \n-\n-\tSQR_ADD_C a0L,a0R,c1,c2,c3\n-\tSTD c1,0(r_ptr) ; r[0] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C2 a1L,a1R,a0L,a0R,c2,c3,c1\n-\tSTD c2,8(r_ptr) ; r[1] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C a1L,a1R,c3,c1,c2\n-\tSQR_ADD_C2 a2L,a2R,a0L,a0R,c3,c1,c2\n-\tSTD c3,16(r_ptr) ; r[2] \u003d c3;\n-\tCOPY %r0,c3\n-\n-\tSQR_ADD_C2 a3L,a3R,a0L,a0R,c1,c2,c3\n-\tSQR_ADD_C2 a2L,a2R,a1L,a1R,c1,c2,c3\n-\tSTD c1,24(r_ptr) ; r[3] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C a2L,a2R,c2,c3,c1\n-\tSQR_ADD_C2 a3L,a3R,a1L,a1R,c2,c3,c1\n-\tSQR_ADD_C2 a4L,a4R,a0L,a0R,c2,c3,c1\n-\tSTD c2,32(r_ptr) ; r[4] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C2 a5L,a5R,a0L,a0R,c3,c1,c2\n-\tSQR_ADD_C2 a4L,a4R,a1L,a1R,c3,c1,c2\n-\tSQR_ADD_C2 a3L,a3R,a2L,a2R,c3,c1,c2\n-\tSTD c3,40(r_ptr) ; r[5] \u003d c3;\n-\tCOPY %r0,c3\n-\n-\tSQR_ADD_C a3L,a3R,c1,c2,c3\n-\tSQR_ADD_C2 a4L,a4R,a2L,a2R,c1,c2,c3\n-\tSQR_ADD_C2 a5L,a5R,a1L,a1R,c1,c2,c3\n-\tSQR_ADD_C2 a6L,a6R,a0L,a0R,c1,c2,c3\n-\tSTD c1,48(r_ptr) ; r[6] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C2 a7L,a7R,a0L,a0R,c2,c3,c1\n-\tSQR_ADD_C2 a6L,a6R,a1L,a1R,c2,c3,c1\n-\tSQR_ADD_C2 a5L,a5R,a2L,a2R,c2,c3,c1\n-\tSQR_ADD_C2 a4L,a4R,a3L,a3R,c2,c3,c1\n-\tSTD c2,56(r_ptr) ; r[7] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C a4L,a4R,c3,c1,c2\n-\tSQR_ADD_C2 a5L,a5R,a3L,a3R,c3,c1,c2\n-\tSQR_ADD_C2 a6L,a6R,a2L,a2R,c3,c1,c2\n-\tSQR_ADD_C2 a7L,a7R,a1L,a1R,c3,c1,c2\n-\tSTD c3,64(r_ptr) ; r[8] \u003d c3;\n-\tCOPY %r0,c3\n-\n-\tSQR_ADD_C2 a7L,a7R,a2L,a2R,c1,c2,c3\n-\tSQR_ADD_C2 a6L,a6R,a3L,a3R,c1,c2,c3\n-\tSQR_ADD_C2 a5L,a5R,a4L,a4R,c1,c2,c3\n-\tSTD c1,72(r_ptr) ; r[9] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C a5L,a5R,c2,c3,c1\n-\tSQR_ADD_C2 a6L,a6R,a4L,a4R,c2,c3,c1\n-\tSQR_ADD_C2 a7L,a7R,a3L,a3R,c2,c3,c1\n-\tSTD c2,80(r_ptr) ; r[10] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C2 a7L,a7R,a4L,a4R,c3,c1,c2\n-\tSQR_ADD_C2 a6L,a6R,a5L,a5R,c3,c1,c2\n-\tSTD c3,88(r_ptr) ; r[11] \u003d c3;\n-\tCOPY %r0,c3\n-\t\n-\tSQR_ADD_C a6L,a6R,c1,c2,c3\n-\tSQR_ADD_C2 a7L,a7R,a5L,a5R,c1,c2,c3\n-\tSTD c1,96(r_ptr) ; r[12] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C2 a7L,a7R,a6L,a6R,c2,c3,c1\n-\tSTD c2,104(r_ptr) ; r[13] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C a7L,a7R,c3,c1,c2\n-\tSTD c3, 112(r_ptr) ; r[14] \u003d c3\n-\tSTD c1, 120(r_ptr) ; r[15] \u003d c1\n-\n- .EXIT\n- LDD -104(%sp),%r6 ; restore r6\n- LDD -112(%sp),%r5 ; restore r5\n- LDD -120(%sp),%r4 ; restore r4\n- BVE (%rp)\n- LDD,MB -128(%sp),%r3\n-\n-\t.PROCEND\t\n-\n-;-----------------------------------------------------------------------------\n-;\n-;void bn_sqr_comba4(BN_ULONG *r, BN_ULONG *a)\n-; arg0 \u003d r_ptr\n-; arg1 \u003d a_ptr\n-;\n-\n-bn_sqr_comba4\n-\t.proc\n-\t.callinfo FRAME\u003d128,ENTRY_GR\u003d%r3,ARGS_SAVED,ORDERING_AWARE\n-\t.EXPORT\tbn_sqr_comba4,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .entry\n-\t.align 64\n- STD %r3,0(%sp) ; save r3\n- STD %r4,8(%sp) ; save r4\n- STD %r5,16(%sp) ; save r5\n- STD %r6,24(%sp) ; save r6\n-\n-\t;\n-\t; Zero out carries\n-\t;\n-\tCOPY %r0,c1\n-\tCOPY %r0,c2\n-\tCOPY %r0,c3\n-\n-\tLDO 128(%sp),%sp ; bump stack\n- DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L\n- DEPDI,Z 1,31,1,high_one ; Create Value 1 \u003c\u003c 32\n-\n-\t;\n-\t; Load up all of the values we are going to use\n-\t;\n- FLDD 0(a_ptr),a0 \n- FLDD 8(a_ptr),a1 \n- FLDD 16(a_ptr),a2 \n- FLDD 24(a_ptr),a3 \n- FLDD 32(a_ptr),a4 \n- FLDD 40(a_ptr),a5 \n- FLDD 48(a_ptr),a6 \n- FLDD 56(a_ptr),a7 \n-\n-\tSQR_ADD_C a0L,a0R,c1,c2,c3\n-\n-\tSTD c1,0(r_ptr) ; r[0] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C2 a1L,a1R,a0L,a0R,c2,c3,c1\n-\n-\tSTD c2,8(r_ptr) ; r[1] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C a1L,a1R,c3,c1,c2\n-\tSQR_ADD_C2 a2L,a2R,a0L,a0R,c3,c1,c2\n-\n-\tSTD c3,16(r_ptr) ; r[2] \u003d c3;\n-\tCOPY %r0,c3\n-\n-\tSQR_ADD_C2 a3L,a3R,a0L,a0R,c1,c2,c3\n-\tSQR_ADD_C2 a2L,a2R,a1L,a1R,c1,c2,c3\n-\n-\tSTD c1,24(r_ptr) ; r[3] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C a2L,a2R,c2,c3,c1\n-\tSQR_ADD_C2 a3L,a3R,a1L,a1R,c2,c3,c1\n-\n-\tSTD c2,32(r_ptr) ; r[4] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C2 a3L,a3R,a2L,a2R,c3,c1,c2\n-\tSTD c3,40(r_ptr) ; r[5] \u003d c3;\n-\tCOPY %r0,c3\n-\n-\tSQR_ADD_C a3L,a3R,c1,c2,c3\n-\tSTD c1,48(r_ptr) ; r[6] \u003d c1;\n-\tSTD c2,56(r_ptr) ; r[7] \u003d c2;\n-\n- .EXIT\n- LDD -104(%sp),%r6 ; restore r6\n- LDD -112(%sp),%r5 ; restore r5\n- LDD -120(%sp),%r4 ; restore r4\n- BVE (%rp)\n- LDD,MB -128(%sp),%r3\n-\n-\t.PROCEND\t\n-\n-\n-;---------------------------------------------------------------------------\n-\n-MUL_ADD_C .macro A0L,A0R,B0L,B0R,C1,C2,C3\n- XMPYU A0L,B0R,ftemp1 ; m1 \u003d bl*ht\n- FSTD ftemp1,-16(%sp) ;\n- XMPYU A0R,B0L,ftemp2 ; m \u003d bh*lt\n- FSTD ftemp2,-8(%sp) ;\n- XMPYU A0R,B0R,ftemp3 ; lt \u003d bl*lt\n- FSTD ftemp3,-32(%sp)\n- XMPYU A0L,B0L,ftemp4 ; ht \u003d bh*ht\n- FSTD ftemp4,-24(%sp) ;\n-\n- LDD -8(%sp),m ; r21 \u003d m\n- LDD -16(%sp),m1 ; r19 \u003d m1\n- ADD,L m,m1,m ; m+m1\n-\n- DEPD,Z m,31,32,temp3 ; (m+m1\u003c\u003c32)\n- LDD -24(%sp),ht ; r24 \u003d ht\n-\n- CMPCLR,*\u003e\u003e\u003d m,m1,%r0 ; if (m \u003c m1)\n- ADD,L ht,high_one,ht ; ht+\u003dhigh_one\n-\n- EXTRD,U m,31,32,temp1 ; m \u003e\u003e 32\n- LDD -32(%sp),lt ; lt\n- ADD,L ht,temp1,ht ; ht+\u003d m\u003e\u003e32\n- ADD lt,temp3,lt ; lt \u003d lt+m1\n- ADD,DC ht,%r0,ht ; ht++\n-\n- ADD C1,lt,C1 ; c1\u003dc1+lt\n- ADD,DC ht,%r0,ht ; bump c3 if overflow,nullify otherwise\n-\n- ADD C2,ht,C2 ; c2 \u003d c2 + ht\n- ADD,DC C3,%r0,C3 ; add in carry (c3++)\n-.endm\n-\n-\n-;\n-;void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)\n-; arg0 \u003d r_ptr\n-; arg1 \u003d a_ptr\n-; arg2 \u003d b_ptr\n-;\n-\n-bn_mul_comba8\n-\t.proc\n-\t.callinfo FRAME\u003d128,ENTRY_GR\u003d%r3,ARGS_SAVED,ORDERING_AWARE\n-\t.EXPORT\tbn_mul_comba8,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .entry\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3\n- STD %r4,8(%sp) ; save r4\n- STD %r5,16(%sp) ; save r5\n- STD %r6,24(%sp) ; save r6\n- FSTD %fr12,32(%sp) ; save r6\n- FSTD %fr13,40(%sp) ; save r7\n-\n-\t;\n-\t; Zero out carries\n-\t;\n-\tCOPY %r0,c1\n-\tCOPY %r0,c2\n-\tCOPY %r0,c3\n-\n-\tLDO 128(%sp),%sp ; bump stack\n- DEPDI,Z 1,31,1,high_one ; Create Value 1 \u003c\u003c 32\n-\n-\t;\n-\t; Load up all of the values we are going to use\n-\t;\n- FLDD 0(a_ptr),a0 \n- FLDD 8(a_ptr),a1 \n- FLDD 16(a_ptr),a2 \n- FLDD 24(a_ptr),a3 \n- FLDD 32(a_ptr),a4 \n- FLDD 40(a_ptr),a5 \n- FLDD 48(a_ptr),a6 \n- FLDD 56(a_ptr),a7 \n-\n- FLDD 0(b_ptr),b0 \n- FLDD 8(b_ptr),b1 \n- FLDD 16(b_ptr),b2 \n- FLDD 24(b_ptr),b3 \n- FLDD 32(b_ptr),b4 \n- FLDD 40(b_ptr),b5 \n- FLDD 48(b_ptr),b6 \n- FLDD 56(b_ptr),b7 \n-\n-\tMUL_ADD_C a0L,a0R,b0L,b0R,c1,c2,c3\n-\tSTD c1,0(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a0L,a0R,b1L,b1R,c2,c3,c1\n-\tMUL_ADD_C a1L,a1R,b0L,b0R,c2,c3,c1\n-\tSTD c2,8(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a2L,a2R,b0L,b0R,c3,c1,c2\n-\tMUL_ADD_C a1L,a1R,b1L,b1R,c3,c1,c2\n-\tMUL_ADD_C a0L,a0R,b2L,b2R,c3,c1,c2\n-\tSTD c3,16(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a0L,a0R,b3L,b3R,c1,c2,c3\n-\tMUL_ADD_C a1L,a1R,b2L,b2R,c1,c2,c3\n-\tMUL_ADD_C a2L,a2R,b1L,b1R,c1,c2,c3\n-\tMUL_ADD_C a3L,a3R,b0L,b0R,c1,c2,c3\n-\tSTD c1,24(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a4L,a4R,b0L,b0R,c2,c3,c1\n-\tMUL_ADD_C a3L,a3R,b1L,b1R,c2,c3,c1\n-\tMUL_ADD_C a2L,a2R,b2L,b2R,c2,c3,c1\n-\tMUL_ADD_C a1L,a1R,b3L,b3R,c2,c3,c1\n-\tMUL_ADD_C a0L,a0R,b4L,b4R,c2,c3,c1\n-\tSTD c2,32(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a0L,a0R,b5L,b5R,c3,c1,c2\n-\tMUL_ADD_C a1L,a1R,b4L,b4R,c3,c1,c2\n-\tMUL_ADD_C a2L,a2R,b3L,b3R,c3,c1,c2\n-\tMUL_ADD_C a3L,a3R,b2L,b2R,c3,c1,c2\n-\tMUL_ADD_C a4L,a4R,b1L,b1R,c3,c1,c2\n-\tMUL_ADD_C a5L,a5R,b0L,b0R,c3,c1,c2\n-\tSTD c3,40(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a6L,a6R,b0L,b0R,c1,c2,c3\n-\tMUL_ADD_C a5L,a5R,b1L,b1R,c1,c2,c3\n-\tMUL_ADD_C a4L,a4R,b2L,b2R,c1,c2,c3\n-\tMUL_ADD_C a3L,a3R,b3L,b3R,c1,c2,c3\n-\tMUL_ADD_C a2L,a2R,b4L,b4R,c1,c2,c3\n-\tMUL_ADD_C a1L,a1R,b5L,b5R,c1,c2,c3\n-\tMUL_ADD_C a0L,a0R,b6L,b6R,c1,c2,c3\n-\tSTD c1,48(r_ptr)\n-\tCOPY %r0,c1\n-\t\n-\tMUL_ADD_C a0L,a0R,b7L,b7R,c2,c3,c1\n-\tMUL_ADD_C a1L,a1R,b6L,b6R,c2,c3,c1\n-\tMUL_ADD_C a2L,a2R,b5L,b5R,c2,c3,c1\n-\tMUL_ADD_C a3L,a3R,b4L,b4R,c2,c3,c1\n-\tMUL_ADD_C a4L,a4R,b3L,b3R,c2,c3,c1\n-\tMUL_ADD_C a5L,a5R,b2L,b2R,c2,c3,c1\n-\tMUL_ADD_C a6L,a6R,b1L,b1R,c2,c3,c1\n-\tMUL_ADD_C a7L,a7R,b0L,b0R,c2,c3,c1\n-\tSTD c2,56(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a7L,a7R,b1L,b1R,c3,c1,c2\n-\tMUL_ADD_C a6L,a6R,b2L,b2R,c3,c1,c2\n-\tMUL_ADD_C a5L,a5R,b3L,b3R,c3,c1,c2\n-\tMUL_ADD_C a4L,a4R,b4L,b4R,c3,c1,c2\n-\tMUL_ADD_C a3L,a3R,b5L,b5R,c3,c1,c2\n-\tMUL_ADD_C a2L,a2R,b6L,b6R,c3,c1,c2\n-\tMUL_ADD_C a1L,a1R,b7L,b7R,c3,c1,c2\n-\tSTD c3,64(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a2L,a2R,b7L,b7R,c1,c2,c3\n-\tMUL_ADD_C a3L,a3R,b6L,b6R,c1,c2,c3\n-\tMUL_ADD_C a4L,a4R,b5L,b5R,c1,c2,c3\n-\tMUL_ADD_C a5L,a5R,b4L,b4R,c1,c2,c3\n-\tMUL_ADD_C a6L,a6R,b3L,b3R,c1,c2,c3\n-\tMUL_ADD_C a7L,a7R,b2L,b2R,c1,c2,c3\n-\tSTD c1,72(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a7L,a7R,b3L,b3R,c2,c3,c1\n-\tMUL_ADD_C a6L,a6R,b4L,b4R,c2,c3,c1\n-\tMUL_ADD_C a5L,a5R,b5L,b5R,c2,c3,c1\n-\tMUL_ADD_C a4L,a4R,b6L,b6R,c2,c3,c1\n-\tMUL_ADD_C a3L,a3R,b7L,b7R,c2,c3,c1\n-\tSTD c2,80(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a4L,a4R,b7L,b7R,c3,c1,c2\n-\tMUL_ADD_C a5L,a5R,b6L,b6R,c3,c1,c2\n-\tMUL_ADD_C a6L,a6R,b5L,b5R,c3,c1,c2\n-\tMUL_ADD_C a7L,a7R,b4L,b4R,c3,c1,c2\n-\tSTD c3,88(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a7L,a7R,b5L,b5R,c1,c2,c3\n-\tMUL_ADD_C a6L,a6R,b6L,b6R,c1,c2,c3\n-\tMUL_ADD_C a5L,a5R,b7L,b7R,c1,c2,c3\n-\tSTD c1,96(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a6L,a6R,b7L,b7R,c2,c3,c1\n-\tMUL_ADD_C a7L,a7R,b6L,b6R,c2,c3,c1\n-\tSTD c2,104(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a7L,a7R,b7L,b7R,c3,c1,c2\n-\tSTD c3,112(r_ptr)\n-\tSTD c1,120(r_ptr)\n-\n- .EXIT\n- FLDD -88(%sp),%fr13 \n- FLDD -96(%sp),%fr12 \n- LDD -104(%sp),%r6 ; restore r6\n- LDD -112(%sp),%r5 ; restore r5\n- LDD -120(%sp),%r4 ; restore r4\n- BVE (%rp)\n- LDD,MB -128(%sp),%r3\n-\n-\t.PROCEND\t\n-\n-;-----------------------------------------------------------------------------\n-;\n-;void bn_mul_comba4(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)\n-; arg0 \u003d r_ptr\n-; arg1 \u003d a_ptr\n-; arg2 \u003d b_ptr\n-;\n-\n-bn_mul_comba4\n-\t.proc\n-\t.callinfo FRAME\u003d128,ENTRY_GR\u003d%r3,ARGS_SAVED,ORDERING_AWARE\n-\t.EXPORT\tbn_mul_comba4,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .entry\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3\n- STD %r4,8(%sp) ; save r4\n- STD %r5,16(%sp) ; save r5\n- STD %r6,24(%sp) ; save r6\n- FSTD %fr12,32(%sp) ; save r6\n- FSTD %fr13,40(%sp) ; save r7\n-\n-\t;\n-\t; Zero out carries\n-\t;\n-\tCOPY %r0,c1\n-\tCOPY %r0,c2\n-\tCOPY %r0,c3\n-\n-\tLDO 128(%sp),%sp ; bump stack\n- DEPDI,Z 1,31,1,high_one ; Create Value 1 \u003c\u003c 32\n-\n-\t;\n-\t; Load up all of the values we are going to use\n-\t;\n- FLDD 0(a_ptr),a0 \n- FLDD 8(a_ptr),a1 \n- FLDD 16(a_ptr),a2 \n- FLDD 24(a_ptr),a3 \n-\n- FLDD 0(b_ptr),b0 \n- FLDD 8(b_ptr),b1 \n- FLDD 16(b_ptr),b2 \n- FLDD 24(b_ptr),b3 \n-\n-\tMUL_ADD_C a0L,a0R,b0L,b0R,c1,c2,c3\n-\tSTD c1,0(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a0L,a0R,b1L,b1R,c2,c3,c1\n-\tMUL_ADD_C a1L,a1R,b0L,b0R,c2,c3,c1\n-\tSTD c2,8(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a2L,a2R,b0L,b0R,c3,c1,c2\n-\tMUL_ADD_C a1L,a1R,b1L,b1R,c3,c1,c2\n-\tMUL_ADD_C a0L,a0R,b2L,b2R,c3,c1,c2\n-\tSTD c3,16(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a0L,a0R,b3L,b3R,c1,c2,c3\n-\tMUL_ADD_C a1L,a1R,b2L,b2R,c1,c2,c3\n-\tMUL_ADD_C a2L,a2R,b1L,b1R,c1,c2,c3\n-\tMUL_ADD_C a3L,a3R,b0L,b0R,c1,c2,c3\n-\tSTD c1,24(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a3L,a3R,b1L,b1R,c2,c3,c1\n-\tMUL_ADD_C a2L,a2R,b2L,b2R,c2,c3,c1\n-\tMUL_ADD_C a1L,a1R,b3L,b3R,c2,c3,c1\n-\tSTD c2,32(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a2L,a2R,b3L,b3R,c3,c1,c2\n-\tMUL_ADD_C a3L,a3R,b2L,b2R,c3,c1,c2\n-\tSTD c3,40(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a3L,a3R,b3L,b3R,c1,c2,c3\n-\tSTD c1,48(r_ptr)\n-\tSTD c2,56(r_ptr)\n-\n- .EXIT\n- FLDD -88(%sp),%fr13 \n- FLDD -96(%sp),%fr12 \n- LDD -104(%sp),%r6 ; restore r6\n- LDD -112(%sp),%r5 ; restore r5\n- LDD -120(%sp),%r4 ; restore r4\n- BVE (%rp)\n- LDD,MB -128(%sp),%r3\n-\n-\t.PROCEND\t\n-\n-\n-;--- not PIC\t.SPACE\t$TEXT$\n-;--- not PIC\t.SUBSPA\t$CODE$\n-;--- not PIC\t.SPACE\t$PRIVATE$,SORT\u003d16\n-;--- not PIC\t.IMPORT\t$global$,DATA\n-;--- not PIC\t.SPACE\t$TEXT$\n-;--- not PIC\t.SUBSPA\t$CODE$\n-;--- not PIC\t.SUBSPA\t$LIT$,ACCESS\u003d0x2c\n-;--- not PIC\tC$7\n-;--- not PIC\t.ALIGN\t8\n-;--- not PIC\t.STRINGZ\t\u0022Division would overflow (%d)\u005cn\u0022\n-\t.END\ndiff --git a/crypto/bn/asm/pa-risc2W.s b/crypto/bn/asm/pa-risc2W.s\ndeleted file mode 100644\nindex 9738117..0000000\n--- a/crypto/bn/asm/pa-risc2W.s\n+++ /dev/null\n@@ -1,1612 +0,0 @@\n-; Copyright 2000-2016 The OpenSSL Project Authors. All Rights Reserved.\n-;\n-; Licensed under the OpenSSL license (the \u0022License\u0022). You may not use\n-; this file except in compliance with the License. You can obtain a copy\n-; in the file LICENSE in the source distribution or at\n-; https://www.openssl.org/source/license.html\n-\n-;\n-; PA-RISC 64-bit implementation of bn_asm code\n-;\n-; This code is approximately 2x faster than the C version\n-; for RSA/DSA.\n-;\n-; See http://devresource.hp.com/ for more details on the PA-RISC\n-; architecture. Also see the book \u0022PA-RISC 2.0 Architecture\u0022\n-; by Gerry Kane for information on the instruction set architecture.\n-;\n-; Code written by Chris Ruemmler (with some help from the HP C\n-; compiler).\n-;\n-; The code compiles with HP's assembler\n-;\n-\n-\t.level\t2.0W\n-\t.space\t$TEXT$\n-\t.subspa\t$CODE$,QUAD\u003d0,ALIGN\u003d8,ACCESS\u003d0x2c,CODE_ONLY\n-\n-;\n-; Global Register definitions used for the routines.\n-;\n-; Some information about HP's runtime architecture for 64-bits.\n-;\n-; \u0022Caller save\u0022 means the calling function must save the register\n-; if it wants the register to be preserved.\n-; \u0022Callee save\u0022 means if a function uses the register, it must save\n-; the value before using it.\n-;\n-; For the floating point registers \n-;\n-; \u0022caller save\u0022 registers: fr4-fr11, fr22-fr31\n-; \u0022callee save\u0022 registers: fr12-fr21\n-; \u0022special\u0022 registers: fr0-fr3 (status and exception registers)\n-;\n-; For the integer registers\n-; value zero : r0\n-; \u0022caller save\u0022 registers: r1,r19-r26\n-; \u0022callee save\u0022 registers: r3-r18\n-; return register : r2 (rp)\n-; return values ; r28 (ret0,ret1)\n-; Stack pointer ; r30 (sp) \n-; global data pointer ; r27 (dp)\n-; argument pointer ; r29 (ap)\n-; millicode return ptr ; r31 (also a caller save register)\n-\n-\n-;\n-; Arguments to the routines\n-;\n-r_ptr .reg %r26\n-a_ptr .reg %r25\n-b_ptr .reg %r24\n-num .reg %r24\n-w .reg %r23\n-n .reg %r23\n-\n-\n-;\n-; Globals used in some routines\n-;\n-\n-top_overflow .reg %r29\n-high_mask .reg %r22 ; value 0xffffffff80000000L\n-\n-\n-;------------------------------------------------------------------------------\n-;\n-; bn_mul_add_words\n-;\n-;BN_ULONG bn_mul_add_words(BN_ULONG *r_ptr, BN_ULONG *a_ptr, \n-;\t\t\t\t\t\t\t\tint num, BN_ULONG w)\n-;\n-; arg0 \u003d r_ptr\n-; arg1 \u003d a_ptr\n-; arg2 \u003d num\n-; arg3 \u003d w\n-;\n-; Local register definitions\n-;\n-\n-fm1 .reg %fr22\n-fm .reg %fr23\n-ht_temp .reg %fr24\n-ht_temp_1 .reg %fr25\n-lt_temp .reg %fr26\n-lt_temp_1 .reg %fr27\n-fm1_1 .reg %fr28\n-fm_1 .reg %fr29\n-\n-fw_h .reg %fr7L\n-fw_l .reg %fr7R\n-fw .reg %fr7\n-\n-fht_0 .reg %fr8L\n-flt_0 .reg %fr8R\n-t_float_0 .reg %fr8\n-\n-fht_1 .reg %fr9L\n-flt_1 .reg %fr9R\n-t_float_1 .reg %fr9\n-\n-tmp_0 .reg %r31\n-tmp_1 .reg %r21\n-m_0 .reg %r20 \n-m_1 .reg %r19 \n-ht_0 .reg %r1 \n-ht_1 .reg %r3\n-lt_0 .reg %r4\n-lt_1 .reg %r5\n-m1_0 .reg %r6 \n-m1_1 .reg %r7 \n-rp_val .reg %r8\n-rp_val_1 .reg %r9\n-\n-bn_mul_add_words\n-\t.export\tbn_mul_add_words,entry,NO_RELOCATION,LONG_RETURN\n-\t.proc\n-\t.callinfo frame\u003d128\n- .entry\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3 \n- STD %r4,8(%sp) ; save r4 \n-\tNOP ; Needed to make the loop 16-byte aligned\n-\tNOP ; Needed to make the loop 16-byte aligned\n-\n- STD %r5,16(%sp) ; save r5 \n- STD %r6,24(%sp) ; save r6 \n- STD %r7,32(%sp) ; save r7 \n- STD %r8,40(%sp) ; save r8 \n-\n- STD %r9,48(%sp) ; save r9 \n- COPY %r0,%ret0 ; return 0 by default\n- DEPDI,Z 1,31,1,top_overflow ; top_overflow \u003d 1 \u003c\u003c 32 \n-\tSTD w,56(%sp) ; store w on stack\n-\n- CMPIB,\u003e\u003d 0,num,bn_mul_add_words_exit ; if (num \u003c\u003d 0) then exit\n-\tLDO 128(%sp),%sp ; bump stack\n-\n-\t;\n-\t; The loop is unrolled twice, so if there is only 1 number\n- ; then go straight to the cleanup code.\n-\t;\n-\tCMPIB,\u003d 1,num,bn_mul_add_words_single_top\n-\tFLDD -72(%sp),fw ; load up w into fp register fw (fw_h/fw_l)\n-\n-\t;\n-\t; This loop is unrolled 2 times (64-byte aligned as well)\n-\t;\n-\t; PA-RISC 2.0 chips have two fully pipelined multipliers, thus\n- ; two 32-bit mutiplies can be issued per cycle.\n- ; \n-bn_mul_add_words_unroll2\n-\n- FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n- FLDD 8(a_ptr),t_float_1 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n- LDD 0(r_ptr),rp_val ; rp[0]\n- LDD 8(r_ptr),rp_val_1 ; rp[1]\n-\n- XMPYU fht_0,fw_l,fm1 ; m1[0] \u003d fht_0*fw_l\n- XMPYU fht_1,fw_l,fm1_1 ; m1[1] \u003d fht_1*fw_l\n- FSTD fm1,-16(%sp) ; -16(sp) \u003d m1[0]\n- FSTD fm1_1,-48(%sp) ; -48(sp) \u003d m1[1]\n-\n- XMPYU flt_0,fw_h,fm ; m[0] \u003d flt_0*fw_h\n- XMPYU flt_1,fw_h,fm_1 ; m[1] \u003d flt_1*fw_h\n- FSTD fm,-8(%sp) ; -8(sp) \u003d m[0]\n- FSTD fm_1,-40(%sp) ; -40(sp) \u003d m[1]\n-\n- XMPYU fht_0,fw_h,ht_temp ; ht_temp \u003d fht_0*fw_h\n- XMPYU fht_1,fw_h,ht_temp_1 ; ht_temp_1 \u003d fht_1*fw_h\n- FSTD ht_temp,-24(%sp) ; -24(sp) \u003d ht_temp\n- FSTD ht_temp_1,-56(%sp) ; -56(sp) \u003d ht_temp_1\n-\n- XMPYU flt_0,fw_l,lt_temp ; lt_temp \u003d lt*fw_l\n- XMPYU flt_1,fw_l,lt_temp_1 ; lt_temp \u003d lt*fw_l\n- FSTD lt_temp,-32(%sp) ; -32(sp) \u003d lt_temp \n- FSTD lt_temp_1,-64(%sp) ; -64(sp) \u003d lt_temp_1 \n-\n- LDD -8(%sp),m_0 ; m[0] \n- LDD -40(%sp),m_1 ; m[1]\n- LDD -16(%sp),m1_0 ; m1[0]\n- LDD -48(%sp),m1_1 ; m1[1]\n-\n- LDD -24(%sp),ht_0 ; ht[0]\n- LDD -56(%sp),ht_1 ; ht[1]\n- ADD,L m1_0,m_0,tmp_0 ; tmp_0 \u003d m[0] + m1[0]; \n- ADD,L m1_1,m_1,tmp_1 ; tmp_1 \u003d m[1] + m1[1]; \n-\n- LDD -32(%sp),lt_0 \n- LDD -64(%sp),lt_1 \n- CMPCLR,*\u003e\u003e\u003d tmp_0,m1_0, %r0 ; if (m[0] \u003c m1[0])\n- ADD,L ht_0,top_overflow,ht_0 ; ht[0] +\u003d (1\u003c\u003c32)\n-\n- CMPCLR,*\u003e\u003e\u003d tmp_1,m1_1,%r0 ; if (m[1] \u003c m1[1])\n- ADD,L ht_1,top_overflow,ht_1 ; ht[1] +\u003d (1\u003c\u003c32)\n- EXTRD,U tmp_0,31,32,m_0 ; m[0]\u003e\u003e32 \n- DEPD,Z tmp_0,31,32,m1_0 ; m1[0] \u003d m[0]\u003c\u003c32 \n-\n- EXTRD,U tmp_1,31,32,m_1 ; m[1]\u003e\u003e32 \n- DEPD,Z tmp_1,31,32,m1_1 ; m1[1] \u003d m[1]\u003c\u003c32 \n- ADD,L ht_0,m_0,ht_0 ; ht[0]+\u003d (m[0]\u003e\u003e32)\n- ADD,L ht_1,m_1,ht_1 ; ht[1]+\u003d (m[1]\u003e\u003e32)\n-\n- ADD lt_0,m1_0,lt_0 ; lt[0] \u003d lt[0]+m1[0];\n-\tADD,DC ht_0,%r0,ht_0 ; ht[0]++\n- ADD lt_1,m1_1,lt_1 ; lt[1] \u003d lt[1]+m1[1];\n- ADD,DC ht_1,%r0,ht_1 ; ht[1]++\n-\n- ADD %ret0,lt_0,lt_0 ; lt[0] \u003d lt[0] + c;\n-\tADD,DC ht_0,%r0,ht_0 ; ht[0]++\n- ADD lt_0,rp_val,lt_0 ; lt[0] \u003d lt[0]+rp[0]\n- ADD,DC ht_0,%r0,ht_0 ; ht[0]++\n-\n-\tLDO -2(num),num ; num \u003d num - 2;\n- ADD ht_0,lt_1,lt_1 ; lt[1] \u003d lt[1] + ht_0 (c);\n- ADD,DC ht_1,%r0,ht_1 ; ht[1]++\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt[0]\n-\n- ADD lt_1,rp_val_1,lt_1 ; lt[1] \u003d lt[1]+rp[1]\n- ADD,DC ht_1,%r0,%ret0 ; ht[1]++\n- LDO 16(a_ptr),a_ptr ; a_ptr +\u003d 2\n-\n- STD lt_1,8(r_ptr) ; rp[1] \u003d lt[1]\n-\tCMPIB,\u003c\u003d 2,num,bn_mul_add_words_unroll2 ; go again if more to do\n- LDO 16(r_ptr),r_ptr ; r_ptr +\u003d 2\n-\n- CMPIB,\u003d,N 0,num,bn_mul_add_words_exit ; are we done, or cleanup last one\n-\n-\t;\n-\t; Top of loop aligned on 64-byte boundary\n-\t;\n-bn_mul_add_words_single_top\n- FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n- LDD 0(r_ptr),rp_val ; rp[0]\n- LDO 8(a_ptr),a_ptr ; a_ptr++\n- XMPYU fht_0,fw_l,fm1 ; m1 \u003d ht*fw_l\n- FSTD fm1,-16(%sp) ; -16(sp) \u003d m1\n- XMPYU flt_0,fw_h,fm ; m \u003d lt*fw_h\n- FSTD fm,-8(%sp) ; -8(sp) \u003d m\n- XMPYU fht_0,fw_h,ht_temp ; ht_temp \u003d ht*fw_h\n- FSTD ht_temp,-24(%sp) ; -24(sp) \u003d ht\n- XMPYU flt_0,fw_l,lt_temp ; lt_temp \u003d lt*fw_l\n- FSTD lt_temp,-32(%sp) ; -32(sp) \u003d lt \n-\n- LDD -8(%sp),m_0 \n- LDD -16(%sp),m1_0 ; m1 \u003d temp1 \n- ADD,L m_0,m1_0,tmp_0 ; tmp_0 \u003d m + m1; \n- LDD -24(%sp),ht_0 \n- LDD -32(%sp),lt_0 \n-\n- CMPCLR,*\u003e\u003e\u003d tmp_0,m1_0,%r0 ; if (m \u003c m1)\n- ADD,L ht_0,top_overflow,ht_0 ; ht +\u003d (1\u003c\u003c32)\n-\n- EXTRD,U tmp_0,31,32,m_0 ; m\u003e\u003e32 \n- DEPD,Z tmp_0,31,32,m1_0 ; m1 \u003d m\u003c\u003c32 \n-\n- ADD,L ht_0,m_0,ht_0 ; ht+\u003d (m\u003e\u003e32)\n- ADD lt_0,m1_0,tmp_0 ; tmp_0 \u003d lt+m1;\n- ADD,DC ht_0,%r0,ht_0 ; ht++\n- ADD %ret0,tmp_0,lt_0 ; lt \u003d lt + c;\n- ADD,DC ht_0,%r0,ht_0 ; ht++\n- ADD lt_0,rp_val,lt_0 ; lt \u003d lt+rp[0]\n- ADD,DC ht_0,%r0,%ret0 ; ht++\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt\n-\n-bn_mul_add_words_exit\n- .EXIT\n- LDD -80(%sp),%r9 ; restore r9 \n- LDD -88(%sp),%r8 ; restore r8 \n- LDD -96(%sp),%r7 ; restore r7 \n- LDD -104(%sp),%r6 ; restore r6 \n- LDD -112(%sp),%r5 ; restore r5 \n- LDD -120(%sp),%r4 ; restore r4 \n- BVE (%rp)\n- LDD,MB -128(%sp),%r3 ; restore r3\n-\t.PROCEND\t;in\u003d23,24,25,26,29;out\u003d28;\n-\n-;----------------------------------------------------------------------------\n-;\n-;BN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)\n-;\n-; arg0 \u003d rp\n-; arg1 \u003d ap\n-; arg2 \u003d num\n-; arg3 \u003d w\n-\n-bn_mul_words\n-\t.proc\n-\t.callinfo frame\u003d128\n- .entry\n-\t.EXPORT\tbn_mul_words,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3 \n- STD %r4,8(%sp) ; save r4 \n- STD %r5,16(%sp) ; save r5 \n- STD %r6,24(%sp) ; save r6 \n-\n- STD %r7,32(%sp) ; save r7 \n- COPY %r0,%ret0 ; return 0 by default\n- DEPDI,Z 1,31,1,top_overflow ; top_overflow \u003d 1 \u003c\u003c 32 \n-\tSTD w,56(%sp) ; w on stack\n-\n- CMPIB,\u003e\u003d 0,num,bn_mul_words_exit\n-\tLDO 128(%sp),%sp ; bump stack\n-\n-\t;\n-\t; See if only 1 word to do, thus just do cleanup\n-\t;\n-\tCMPIB,\u003d 1,num,bn_mul_words_single_top\n-\tFLDD -72(%sp),fw ; load up w into fp register fw (fw_h/fw_l)\n-\n-\t;\n-\t; This loop is unrolled 2 times (64-byte aligned as well)\n-\t;\n-\t; PA-RISC 2.0 chips have two fully pipelined multipliers, thus\n- ; two 32-bit mutiplies can be issued per cycle.\n- ; \n-bn_mul_words_unroll2\n-\n- FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n- FLDD 8(a_ptr),t_float_1 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n- XMPYU fht_0,fw_l,fm1 ; m1[0] \u003d fht_0*fw_l\n- XMPYU fht_1,fw_l,fm1_1 ; m1[1] \u003d ht*fw_l\n-\n- FSTD fm1,-16(%sp) ; -16(sp) \u003d m1\n- FSTD fm1_1,-48(%sp) ; -48(sp) \u003d m1\n- XMPYU flt_0,fw_h,fm ; m \u003d lt*fw_h\n- XMPYU flt_1,fw_h,fm_1 ; m \u003d lt*fw_h\n-\n- FSTD fm,-8(%sp) ; -8(sp) \u003d m\n- FSTD fm_1,-40(%sp) ; -40(sp) \u003d m\n- XMPYU fht_0,fw_h,ht_temp ; ht_temp \u003d fht_0*fw_h\n- XMPYU fht_1,fw_h,ht_temp_1 ; ht_temp \u003d ht*fw_h\n-\n- FSTD ht_temp,-24(%sp) ; -24(sp) \u003d ht\n- FSTD ht_temp_1,-56(%sp) ; -56(sp) \u003d ht\n- XMPYU flt_0,fw_l,lt_temp ; lt_temp \u003d lt*fw_l\n- XMPYU flt_1,fw_l,lt_temp_1 ; lt_temp \u003d lt*fw_l\n-\n- FSTD lt_temp,-32(%sp) ; -32(sp) \u003d lt \n- FSTD lt_temp_1,-64(%sp) ; -64(sp) \u003d lt \n- LDD -8(%sp),m_0 \n- LDD -40(%sp),m_1 \n-\n- LDD -16(%sp),m1_0 \n- LDD -48(%sp),m1_1 \n- LDD -24(%sp),ht_0 \n- LDD -56(%sp),ht_1 \n-\n- ADD,L m1_0,m_0,tmp_0 ; tmp_0 \u003d m + m1; \n- ADD,L m1_1,m_1,tmp_1 ; tmp_1 \u003d m + m1; \n- LDD -32(%sp),lt_0 \n- LDD -64(%sp),lt_1 \n-\n- CMPCLR,*\u003e\u003e\u003d tmp_0,m1_0, %r0 ; if (m \u003c m1)\n- ADD,L ht_0,top_overflow,ht_0 ; ht +\u003d (1\u003c\u003c32)\n- CMPCLR,*\u003e\u003e\u003d tmp_1,m1_1,%r0 ; if (m \u003c m1)\n- ADD,L ht_1,top_overflow,ht_1 ; ht +\u003d (1\u003c\u003c32)\n-\n- EXTRD,U tmp_0,31,32,m_0 ; m\u003e\u003e32 \n- DEPD,Z tmp_0,31,32,m1_0 ; m1 \u003d m\u003c\u003c32 \n- EXTRD,U tmp_1,31,32,m_1 ; m\u003e\u003e32 \n- DEPD,Z tmp_1,31,32,m1_1 ; m1 \u003d m\u003c\u003c32 \n-\n- ADD,L ht_0,m_0,ht_0 ; ht+\u003d (m\u003e\u003e32)\n- ADD,L ht_1,m_1,ht_1 ; ht+\u003d (m\u003e\u003e32)\n- ADD lt_0,m1_0,lt_0 ; lt \u003d lt+m1;\n-\tADD,DC ht_0,%r0,ht_0 ; ht++\n-\n- ADD lt_1,m1_1,lt_1 ; lt \u003d lt+m1;\n- ADD,DC ht_1,%r0,ht_1 ; ht++\n- ADD %ret0,lt_0,lt_0 ; lt \u003d lt + c (ret0);\n-\tADD,DC ht_0,%r0,ht_0 ; ht++\n-\n- ADD ht_0,lt_1,lt_1 ; lt \u003d lt + c (ht_0)\n- ADD,DC ht_1,%r0,ht_1 ; ht++\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt\n- STD lt_1,8(r_ptr) ; rp[1] \u003d lt\n-\n-\tCOPY ht_1,%ret0 ; carry \u003d ht\n-\tLDO -2(num),num ; num \u003d num - 2;\n- LDO 16(a_ptr),a_ptr ; ap +\u003d 2\n-\tCMPIB,\u003c\u003d 2,num,bn_mul_words_unroll2\n- LDO 16(r_ptr),r_ptr ; rp++\n-\n- CMPIB,\u003d,N 0,num,bn_mul_words_exit ; are we done?\n-\n-\t;\n-\t; Top of loop aligned on 64-byte boundary\n-\t;\n-bn_mul_words_single_top\n- FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n-\n- XMPYU fht_0,fw_l,fm1 ; m1 \u003d ht*fw_l\n- FSTD fm1,-16(%sp) ; -16(sp) \u003d m1\n- XMPYU flt_0,fw_h,fm ; m \u003d lt*fw_h\n- FSTD fm,-8(%sp) ; -8(sp) \u003d m\n- XMPYU fht_0,fw_h,ht_temp ; ht_temp \u003d ht*fw_h\n- FSTD ht_temp,-24(%sp) ; -24(sp) \u003d ht\n- XMPYU flt_0,fw_l,lt_temp ; lt_temp \u003d lt*fw_l\n- FSTD lt_temp,-32(%sp) ; -32(sp) \u003d lt \n-\n- LDD -8(%sp),m_0 \n- LDD -16(%sp),m1_0 \n- ADD,L m_0,m1_0,tmp_0 ; tmp_0 \u003d m + m1; \n- LDD -24(%sp),ht_0 \n- LDD -32(%sp),lt_0 \n-\n- CMPCLR,*\u003e\u003e\u003d tmp_0,m1_0,%r0 ; if (m \u003c m1)\n- ADD,L ht_0,top_overflow,ht_0 ; ht +\u003d (1\u003c\u003c32)\n-\n- EXTRD,U tmp_0,31,32,m_0 ; m\u003e\u003e32 \n- DEPD,Z tmp_0,31,32,m1_0 ; m1 \u003d m\u003c\u003c32 \n-\n- ADD,L ht_0,m_0,ht_0 ; ht+\u003d (m\u003e\u003e32)\n- ADD lt_0,m1_0,lt_0 ; lt\u003d lt+m1;\n- ADD,DC ht_0,%r0,ht_0 ; ht++\n-\n- ADD %ret0,lt_0,lt_0 ; lt \u003d lt + c;\n- ADD,DC ht_0,%r0,ht_0 ; ht++\n-\n- COPY ht_0,%ret0 ; copy carry\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt\n-\n-bn_mul_words_exit\n- .EXIT\n- LDD -96(%sp),%r7 ; restore r7 \n- LDD -104(%sp),%r6 ; restore r6 \n- LDD -112(%sp),%r5 ; restore r5 \n- LDD -120(%sp),%r4 ; restore r4 \n- BVE (%rp)\n- LDD,MB -128(%sp),%r3 ; restore r3\n-\t.PROCEND\t;in\u003d23,24,25,26,29;out\u003d28;\n-\n-;----------------------------------------------------------------------------\n-;\n-;void bn_sqr_words(BN_ULONG *rp, BN_ULONG *ap, int num)\n-;\n-; arg0 \u003d rp\n-; arg1 \u003d ap\n-; arg2 \u003d num\n-;\n-\n-bn_sqr_words\n-\t.proc\n-\t.callinfo FRAME\u003d128,ENTRY_GR\u003d%r3,ARGS_SAVED,ORDERING_AWARE\n-\t.EXPORT\tbn_sqr_words,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .entry\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3 \n- STD %r4,8(%sp) ; save r4 \n-\tNOP\n- STD %r5,16(%sp) ; save r5 \n-\n- CMPIB,\u003e\u003d 0,num,bn_sqr_words_exit\n-\tLDO 128(%sp),%sp ; bump stack\n-\n-\t;\n-\t; If only 1, the goto straight to cleanup\n-\t;\n-\tCMPIB,\u003d 1,num,bn_sqr_words_single_top\n- DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L\n-\n-\t;\n-\t; This loop is unrolled 2 times (64-byte aligned as well)\n-\t;\n-\n-bn_sqr_words_unroll2\n- FLDD 0(a_ptr),t_float_0 ; a[0]\n- FLDD 8(a_ptr),t_float_1 ; a[1]\n- XMPYU fht_0,flt_0,fm ; m[0]\n- XMPYU fht_1,flt_1,fm_1 ; m[1]\n-\n- FSTD fm,-24(%sp) ; store m[0]\n- FSTD fm_1,-56(%sp) ; store m[1]\n- XMPYU flt_0,flt_0,lt_temp ; lt[0]\n- XMPYU flt_1,flt_1,lt_temp_1 ; lt[1]\n-\n- FSTD lt_temp,-16(%sp) ; store lt[0]\n- FSTD lt_temp_1,-48(%sp) ; store lt[1]\n- XMPYU fht_0,fht_0,ht_temp ; ht[0]\n- XMPYU fht_1,fht_1,ht_temp_1 ; ht[1]\n-\n- FSTD ht_temp,-8(%sp) ; store ht[0]\n- FSTD ht_temp_1,-40(%sp) ; store ht[1]\n- LDD -24(%sp),m_0 \n- LDD -56(%sp),m_1 \n-\n- AND m_0,high_mask,tmp_0 ; m[0] \u0026 Mask\n- AND m_1,high_mask,tmp_1 ; m[1] \u0026 Mask\n- DEPD,Z m_0,30,31,m_0 ; m[0] \u003c\u003c 32+1\n- DEPD,Z m_1,30,31,m_1 ; m[1] \u003c\u003c 32+1\n-\n- LDD -16(%sp),lt_0 \n- LDD -48(%sp),lt_1 \n- EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 \u003d m[0]\u0026Mask \u003e\u003e 32-1\n- EXTRD,U tmp_1,32,33,tmp_1 ; tmp_1 \u003d m[1]\u0026Mask \u003e\u003e 32-1\n-\n- LDD -8(%sp),ht_0 \n- LDD -40(%sp),ht_1 \n- ADD,L ht_0,tmp_0,ht_0 ; ht[0] +\u003d tmp_0\n- ADD,L ht_1,tmp_1,ht_1 ; ht[1] +\u003d tmp_1\n-\n- ADD lt_0,m_0,lt_0 ; lt \u003d lt+m\n- ADD,DC ht_0,%r0,ht_0 ; ht[0]++\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt[0]\n- STD ht_0,8(r_ptr) ; rp[1] \u003d ht[1]\n-\n- ADD lt_1,m_1,lt_1 ; lt \u003d lt+m\n- ADD,DC ht_1,%r0,ht_1 ; ht[1]++\n- STD lt_1,16(r_ptr) ; rp[2] \u003d lt[1]\n- STD ht_1,24(r_ptr) ; rp[3] \u003d ht[1]\n-\n-\tLDO -2(num),num ; num \u003d num - 2;\n- LDO 16(a_ptr),a_ptr ; ap +\u003d 2\n-\tCMPIB,\u003c\u003d 2,num,bn_sqr_words_unroll2\n- LDO 32(r_ptr),r_ptr ; rp +\u003d 4\n-\n- CMPIB,\u003d,N 0,num,bn_sqr_words_exit ; are we done?\n-\n-\t;\n-\t; Top of loop aligned on 64-byte boundary\n-\t;\n-bn_sqr_words_single_top\n- FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)\n-\n- XMPYU fht_0,flt_0,fm ; m\n- FSTD fm,-24(%sp) ; store m\n-\n- XMPYU flt_0,flt_0,lt_temp ; lt\n- FSTD lt_temp,-16(%sp) ; store lt\n-\n- XMPYU fht_0,fht_0,ht_temp ; ht\n- FSTD ht_temp,-8(%sp) ; store ht\n-\n- LDD -24(%sp),m_0 ; load m\n- AND m_0,high_mask,tmp_0 ; m \u0026 Mask\n- DEPD,Z m_0,30,31,m_0 ; m \u003c\u003c 32+1\n- LDD -16(%sp),lt_0 ; lt\n-\n- LDD -8(%sp),ht_0 ; ht\n- EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 \u003d m\u0026Mask \u003e\u003e 32-1\n- ADD m_0,lt_0,lt_0 ; lt \u003d lt+m\n- ADD,L ht_0,tmp_0,ht_0 ; ht +\u003d tmp_0\n- ADD,DC ht_0,%r0,ht_0 ; ht++\n-\n- STD lt_0,0(r_ptr) ; rp[0] \u003d lt\n- STD ht_0,8(r_ptr) ; rp[1] \u003d ht\n-\n-bn_sqr_words_exit\n- .EXIT\n- LDD -112(%sp),%r5 ; restore r5 \n- LDD -120(%sp),%r4 ; restore r4 \n- BVE (%rp)\n- LDD,MB -128(%sp),%r3 \n-\t.PROCEND\t;in\u003d23,24,25,26,29;out\u003d28;\n-\n-\n-;----------------------------------------------------------------------------\n-;\n-;BN_ULONG bn_add_words(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b, int n)\n-;\n-; arg0 \u003d rp \n-; arg1 \u003d ap\n-; arg2 \u003d bp \n-; arg3 \u003d n\n-\n-t .reg %r22\n-b .reg %r21\n-l .reg %r20\n-\n-bn_add_words\n-\t.proc\n- .entry\n-\t.callinfo\n-\t.EXPORT\tbn_add_words,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n-\t.align 64\n-\n- CMPIB,\u003e\u003d 0,n,bn_add_words_exit\n- COPY %r0,%ret0 ; return 0 by default\n-\n-\t;\n-\t; If 2 or more numbers do the loop\n-\t;\n-\tCMPIB,\u003d 1,n,bn_add_words_single_top\n-\tNOP\n-\n-\t;\n-\t; This loop is unrolled 2 times (64-byte aligned as well)\n-\t;\n-bn_add_words_unroll2\n-\tLDD 0(a_ptr),t\n-\tLDD 0(b_ptr),b\n-\tADD t,%ret0,t ; t \u003d t+c;\n-\tADD,DC %r0,%r0,%ret0 ; set c to carry\n-\tADD t,b,l ; l \u003d t + b[0]\n-\tADD,DC %ret0,%r0,%ret0 ; c+\u003d carry\n-\tSTD l,0(r_ptr)\n-\n-\tLDD 8(a_ptr),t\n-\tLDD 8(b_ptr),b\n-\tADD t,%ret0,t ; t \u003d t+c;\n-\tADD,DC %r0,%r0,%ret0 ; set c to carry\n-\tADD t,b,l ; l \u003d t + b[0]\n-\tADD,DC %ret0,%r0,%ret0 ; c+\u003d carry\n-\tSTD l,8(r_ptr)\n-\n-\tLDO -2(n),n\n-\tLDO 16(a_ptr),a_ptr\n-\tLDO 16(b_ptr),b_ptr\n-\n-\tCMPIB,\u003c\u003d 2,n,bn_add_words_unroll2\n-\tLDO 16(r_ptr),r_ptr\n-\n- CMPIB,\u003d,N 0,n,bn_add_words_exit ; are we done?\n-\n-bn_add_words_single_top\n-\tLDD 0(a_ptr),t\n-\tLDD 0(b_ptr),b\n-\n-\tADD t,%ret0,t ; t \u003d t+c;\n-\tADD,DC %r0,%r0,%ret0 ; set c to carry (could use CMPCLR??)\n-\tADD t,b,l ; l \u003d t + b[0]\n-\tADD,DC %ret0,%r0,%ret0 ; c+\u003d carry\n-\tSTD l,0(r_ptr)\n-\n-bn_add_words_exit\n- .EXIT\n- BVE (%rp)\n-\tNOP\n-\t.PROCEND\t;in\u003d23,24,25,26,29;out\u003d28;\n-\n-;----------------------------------------------------------------------------\n-;\n-;BN_ULONG bn_sub_words(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b, int n)\n-;\n-; arg0 \u003d rp \n-; arg1 \u003d ap\n-; arg2 \u003d bp \n-; arg3 \u003d n\n-\n-t1 .reg %r22\n-t2 .reg %r21\n-sub_tmp1 .reg %r20\n-sub_tmp2 .reg %r19\n-\n-\n-bn_sub_words\n-\t.proc\n-\t.callinfo \n-\t.EXPORT\tbn_sub_words,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .entry\n-\t.align 64\n-\n- CMPIB,\u003e\u003d 0,n,bn_sub_words_exit\n- COPY %r0,%ret0 ; return 0 by default\n-\n-\t;\n-\t; If 2 or more numbers do the loop\n-\t;\n-\tCMPIB,\u003d 1,n,bn_sub_words_single_top\n-\tNOP\n-\n-\t;\n-\t; This loop is unrolled 2 times (64-byte aligned as well)\n-\t;\n-bn_sub_words_unroll2\n-\tLDD 0(a_ptr),t1\n-\tLDD 0(b_ptr),t2\n-\tSUB t1,t2,sub_tmp1 ; t3 \u003d t1-t2; \n-\tSUB sub_tmp1,%ret0,sub_tmp1 ; t3 \u003d t3- c; \n-\n-\tCMPCLR,*\u003e\u003e t1,t2,sub_tmp2 ; clear if t1 \u003e t2\n-\tLDO 1(%r0),sub_tmp2\n-\t\n-\tCMPCLR,*\u003d t1,t2,%r0\n-\tCOPY sub_tmp2,%ret0\n-\tSTD sub_tmp1,0(r_ptr)\n-\n-\tLDD 8(a_ptr),t1\n-\tLDD 8(b_ptr),t2\n-\tSUB t1,t2,sub_tmp1 ; t3 \u003d t1-t2; \n-\tSUB sub_tmp1,%ret0,sub_tmp1 ; t3 \u003d t3- c; \n-\tCMPCLR,*\u003e\u003e t1,t2,sub_tmp2 ; clear if t1 \u003e t2\n-\tLDO 1(%r0),sub_tmp2\n-\t\n-\tCMPCLR,*\u003d t1,t2,%r0\n-\tCOPY sub_tmp2,%ret0\n-\tSTD sub_tmp1,8(r_ptr)\n-\n-\tLDO -2(n),n\n-\tLDO 16(a_ptr),a_ptr\n-\tLDO 16(b_ptr),b_ptr\n-\n-\tCMPIB,\u003c\u003d 2,n,bn_sub_words_unroll2\n-\tLDO 16(r_ptr),r_ptr\n-\n- CMPIB,\u003d,N 0,n,bn_sub_words_exit ; are we done?\n-\n-bn_sub_words_single_top\n-\tLDD 0(a_ptr),t1\n-\tLDD 0(b_ptr),t2\n-\tSUB t1,t2,sub_tmp1 ; t3 \u003d t1-t2; \n-\tSUB sub_tmp1,%ret0,sub_tmp1 ; t3 \u003d t3- c; \n-\tCMPCLR,*\u003e\u003e t1,t2,sub_tmp2 ; clear if t1 \u003e t2\n-\tLDO 1(%r0),sub_tmp2\n-\t\n-\tCMPCLR,*\u003d t1,t2,%r0\n-\tCOPY sub_tmp2,%ret0\n-\n-\tSTD sub_tmp1,0(r_ptr)\n-\n-bn_sub_words_exit\n- .EXIT\n- BVE (%rp)\n-\tNOP\n-\t.PROCEND\t;in\u003d23,24,25,26,29;out\u003d28;\n-\n-;------------------------------------------------------------------------------\n-;\n-; unsigned long bn_div_words(unsigned long h, unsigned long l, unsigned long d)\n-;\n-; arg0 \u003d h\n-; arg1 \u003d l\n-; arg2 \u003d d\n-;\n-; This is mainly just modified assembly from the compiler, thus the\n-; lack of variable names.\n-;\n-;------------------------------------------------------------------------------\n-bn_div_words\n-\t.proc\n-\t.callinfo CALLER,FRAME\u003d272,ENTRY_GR\u003d%r10,SAVE_RP,ARGS_SAVED,ORDERING_AWARE\n-\t.EXPORT\tbn_div_words,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n-\t.IMPORT\tBN_num_bits_word,CODE,NO_RELOCATION\n-\t.IMPORT\t__iob,DATA\n-\t.IMPORT\tfprintf,CODE,NO_RELOCATION\n-\t.IMPORT\tabort,CODE,NO_RELOCATION\n-\t.IMPORT\t$$div2U,MILLICODE\n- .entry\n- STD %r2,-16(%r30) \n- STD,MA %r3,352(%r30) \n- STD %r4,-344(%r30) \n- STD %r5,-336(%r30) \n- STD %r6,-328(%r30) \n- STD %r7,-320(%r30) \n- STD %r8,-312(%r30) \n- STD %r9,-304(%r30) \n- STD %r10,-296(%r30)\n-\n- STD %r27,-288(%r30) ; save gp\n-\n- COPY %r24,%r3 ; save d \n- COPY %r26,%r4 ; save h (high 64-bits)\n- LDO -1(%r0),%ret0 ; return -1 by default\t\n-\n- CMPB,*\u003d %r0,%arg2,$D3 ; if (d \u003d\u003d 0)\n- COPY %r25,%r5 ; save l (low 64-bits)\n-\n- LDO -48(%r30),%r29 ; create ap \n- .CALL ;in\u003d26,29;out\u003d28;\n- B,L BN_num_bits_word,%r2 \n- COPY %r3,%r26 \n- LDD -288(%r30),%r27 ; restore gp \n- LDI 64,%r21 \n-\n- CMPB,\u003d %r21,%ret0,$00000012 ;if (i \u003d\u003d 64) (forward) \n- COPY %ret0,%r24 ; i \n- MTSARCM %r24 \n- DEPDI,Z -1,%sar,1,%r29 \n- CMPB,*\u003c\u003c,N %r29,%r4,bn_div_err_case ; if (h \u003e 1\u003c\u003ci) (forward) \n-\n-$00000012\n- SUBI 64,%r24,%r31 ; i \u003d 64 - i;\n- CMPCLR,*\u003c\u003c %r4,%r3,%r0 ; if (h \u003e\u003d d)\n- SUB %r4,%r3,%r4 ; h -\u003d d\n- CMPB,\u003d %r31,%r0,$0000001A ; if (i)\n- COPY %r0,%r10 ; ret \u003d 0\n- MTSARCM %r31 ; i to shift\n- DEPD,Z %r3,%sar,64,%r3 ; d \u003c\u003c\u003d i;\n- SUBI 64,%r31,%r19 ; 64 - i; redundent\n- MTSAR %r19 ; (64 -i) to shift\n- SHRPD %r4,%r5,%sar,%r4 ; l\u003e\u003e (64-i)\n- MTSARCM %r31 ; i to shift\n- DEPD,Z %r5,%sar,64,%r5 ; l \u003c\u003c\u003d i;\n-\n-$0000001A\n- DEPDI,Z -1,31,32,%r19 \n- EXTRD,U %r3,31,32,%r6 ; dh\u003d(d\u00260xfff)\u003e\u003e32\n- EXTRD,U %r3,63,32,%r8 ; dl \u003d d\u00260xffffff\n- LDO 2(%r0),%r9\n- STD %r3,-280(%r30) ; \u0022d\u0022 to stack\n-\n-$0000001C\n- DEPDI,Z -1,63,32,%r29 ; \n- EXTRD,U %r4,31,32,%r31 ; h \u003e\u003e 32\n- CMPB,*\u003d,N %r31,%r6,$D2 \t ; if ((h\u003e\u003e32) !\u003d dh)(forward) div\n- COPY %r4,%r26 \n- EXTRD,U %r4,31,32,%r25 \n- COPY %r6,%r24 \n- .CALL ;in\u003d23,24,25,26;out\u003d20,21,22,28,29; (MILLICALL)\n- B,L $$div2U,%r2 \n- EXTRD,U %r6,31,32,%r23 \n- DEPD %r28,31,32,%r29 \n-$D2\n- STD %r29,-272(%r30) ; q\n- AND %r5,%r19,%r24 ; t \u0026 0xffffffff00000000;\n- EXTRD,U %r24,31,32,%r24 ; ??? \n- FLDD -272(%r30),%fr7 ; q\n- FLDD -280(%r30),%fr8 ; d\n- XMPYU %fr8L,%fr7L,%fr10 \n- FSTD %fr10,-256(%r30) \n- XMPYU %fr8L,%fr7R,%fr22 \n- FSTD %fr22,-264(%r30) \n- XMPYU %fr8R,%fr7L,%fr11 \n- XMPYU %fr8R,%fr7R,%fr23\n- FSTD %fr11,-232(%r30)\n- FSTD %fr23,-240(%r30)\n- LDD -256(%r30),%r28\n- DEPD,Z %r28,31,32,%r2 \n- LDD -264(%r30),%r20\n- ADD,L %r20,%r2,%r31 \n- LDD -232(%r30),%r22 \n- DEPD,Z %r22,31,32,%r22 \n- LDD -240(%r30),%r21 \n- B $00000024 ; enter loop \n- ADD,L %r21,%r22,%r23 \n-\n-$0000002A\n- LDO -1(%r29),%r29 \n- SUB %r23,%r8,%r23 \n-$00000024\n- SUB %r4,%r31,%r25 \n- AND %r25,%r19,%r26 \n- CMPB,*\u003c\u003e,N %r0,%r26,$00000046 ; (forward)\n- DEPD,Z %r25,31,32,%r20 \n- OR %r20,%r24,%r21 \n- CMPB,*\u003c\u003c,N %r21,%r23,$0000002A ;(backward) \n- SUB %r31,%r6,%r31 \n-;-------------Break path---------------------\n-\n-$00000046\n- DEPD,Z %r23,31,32,%r25 ;tl\n- EXTRD,U %r23,31,32,%r26 ;t\n- AND %r25,%r19,%r24 ;tl \u003d (tl\u003c\u003c32)\u00260xfffffff0000000L\n- ADD,L %r31,%r26,%r31 ;th +\u003d t; \n- CMPCLR,*\u003e\u003e\u003d %r5,%r24,%r0 ;if (l\u003ctl)\n- LDO 1(%r31),%r31 ; th++;\n- CMPB,*\u003c\u003c\u003d,N %r31,%r4,$00000036 ;if (n \u003c th) (forward)\n- LDO -1(%r29),%r29 ;q--; \n- ADD,L %r4,%r3,%r4 ;h +\u003d d;\n-$00000036\n- ADDIB,\u003d,N -1,%r9,$D1 ;if (--count \u003d\u003d 0) break (forward) \n- SUB %r5,%r24,%r28 ; l -\u003d tl;\n- SUB %r4,%r31,%r24 ; h -\u003d th;\n- SHRPD %r24,%r28,32,%r4 ; h \u003d ((h\u003c\u003c32)|(l\u003e\u003e32));\n- DEPD,Z %r29,31,32,%r10 ; ret \u003d q\u003c\u003c32\n- b $0000001C\n- DEPD,Z %r28,31,32,%r5 ; l \u003d l \u003c\u003c 32 \n-\n-$D1\n- OR %r10,%r29,%r28 ; ret |\u003d q\n-$D3\n- LDD -368(%r30),%r2 \n-$D0\n- LDD -296(%r30),%r10 \n- LDD -304(%r30),%r9 \n- LDD -312(%r30),%r8 \n- LDD -320(%r30),%r7 \n- LDD -328(%r30),%r6 \n- LDD -336(%r30),%r5 \n- LDD -344(%r30),%r4 \n- BVE (%r2) \n- .EXIT\n- LDD,MB -352(%r30),%r3 \n-\n-bn_div_err_case\n- MFIA %r6 \n- ADDIL L'bn_div_words-bn_div_err_case,%r6,%r1 \n- LDO R'bn_div_words-bn_div_err_case(%r1),%r6 \n- ADDIL LT'__iob,%r27,%r1 \n- LDD RT'__iob(%r1),%r26 \n- ADDIL L'C$4-bn_div_words,%r6,%r1 \n- LDO R'C$4-bn_div_words(%r1),%r25 \n- LDO 64(%r26),%r26 \n- .CALL ;in\u003d24,25,26,29;out\u003d28;\n- B,L fprintf,%r2 \n- LDO -48(%r30),%r29 \n- LDD -288(%r30),%r27\n- .CALL ;in\u003d29;\n- B,L abort,%r2 \n- LDO -48(%r30),%r29 \n- LDD -288(%r30),%r27\n- B $D0 \n- LDD -368(%r30),%r2 \n-\t.PROCEND\t;in\u003d24,25,26,29;out\u003d28;\n-\n-;----------------------------------------------------------------------------\n-;\n-; Registers to hold 64-bit values to manipulate. The \u0022L\u0022 part\n-; of the register corresponds to the upper 32-bits, while the \u0022R\u0022\n-; part corresponds to the lower 32-bits\n-; \n-; Note, that when using b6 and b7, the code must save these before\n-; using them because they are callee save registers \n-; \n-;\n-; Floating point registers to use to save values that\n-; are manipulated. These don't collide with ftemp1-6 and\n-; are all caller save registers\n-;\n-a0 .reg %fr22\n-a0L .reg %fr22L\n-a0R .reg %fr22R\n-\n-a1 .reg %fr23\n-a1L .reg %fr23L\n-a1R .reg %fr23R\n-\n-a2 .reg %fr24\n-a2L .reg %fr24L\n-a2R .reg %fr24R\n-\n-a3 .reg %fr25\n-a3L .reg %fr25L\n-a3R .reg %fr25R\n-\n-a4 .reg %fr26\n-a4L .reg %fr26L\n-a4R .reg %fr26R\n-\n-a5 .reg %fr27\n-a5L .reg %fr27L\n-a5R .reg %fr27R\n-\n-a6 .reg %fr28\n-a6L .reg %fr28L\n-a6R .reg %fr28R\n-\n-a7 .reg %fr29\n-a7L .reg %fr29L\n-a7R .reg %fr29R\n-\n-b0 .reg %fr30\n-b0L .reg %fr30L\n-b0R .reg %fr30R\n-\n-b1 .reg %fr31\n-b1L .reg %fr31L\n-b1R .reg %fr31R\n-\n-;\n-; Temporary floating point variables, these are all caller save\n-; registers\n-;\n-ftemp1 .reg %fr4\n-ftemp2 .reg %fr5\n-ftemp3 .reg %fr6\n-ftemp4 .reg %fr7\n-\n-;\n-; The B set of registers when used.\n-;\n-\n-b2 .reg %fr8\n-b2L .reg %fr8L\n-b2R .reg %fr8R\n-\n-b3 .reg %fr9\n-b3L .reg %fr9L\n-b3R .reg %fr9R\n-\n-b4 .reg %fr10\n-b4L .reg %fr10L\n-b4R .reg %fr10R\n-\n-b5 .reg %fr11\n-b5L .reg %fr11L\n-b5R .reg %fr11R\n-\n-b6 .reg %fr12\n-b6L .reg %fr12L\n-b6R .reg %fr12R\n-\n-b7 .reg %fr13\n-b7L .reg %fr13L\n-b7R .reg %fr13R\n-\n-c1 .reg %r21 ; only reg\n-temp1 .reg %r20 ; only reg\n-temp2 .reg %r19 ; only reg\n-temp3 .reg %r31 ; only reg\n-\n-m1 .reg %r28 \n-c2 .reg %r23 \n-high_one .reg %r1\n-ht .reg %r6\n-lt .reg %r5\n-m .reg %r4\n-c3 .reg %r3\n-\n-SQR_ADD_C .macro A0L,A0R,C1,C2,C3\n- XMPYU A0L,A0R,ftemp1 ; m\n- FSTD ftemp1,-24(%sp) ; store m\n-\n- XMPYU A0R,A0R,ftemp2 ; lt\n- FSTD ftemp2,-16(%sp) ; store lt\n-\n- XMPYU A0L,A0L,ftemp3 ; ht\n- FSTD ftemp3,-8(%sp) ; store ht\n-\n- LDD -24(%sp),m ; load m\n- AND m,high_mask,temp2 ; m \u0026 Mask\n- DEPD,Z m,30,31,temp3 ; m \u003c\u003c 32+1\n- LDD -16(%sp),lt ; lt\n-\n- LDD -8(%sp),ht ; ht\n- EXTRD,U temp2,32,33,temp1 ; temp1 \u003d m\u0026Mask \u003e\u003e 32-1\n- ADD temp3,lt,lt ; lt \u003d lt+m\n- ADD,L ht,temp1,ht ; ht +\u003d temp1\n- ADD,DC ht,%r0,ht ; ht++\n-\n- ADD C1,lt,C1 ; c1\u003dc1+lt\n- ADD,DC ht,%r0,ht ; ht++\n-\n- ADD C2,ht,C2 ; c2\u003dc2+ht\n- ADD,DC C3,%r0,C3 ; c3++\n-.endm\n-\n-SQR_ADD_C2 .macro A0L,A0R,A1L,A1R,C1,C2,C3\n- XMPYU A0L,A1R,ftemp1 ; m1 \u003d bl*ht\n- FSTD ftemp1,-16(%sp) ;\n- XMPYU A0R,A1L,ftemp2 ; m \u003d bh*lt\n- FSTD ftemp2,-8(%sp) ;\n- XMPYU A0R,A1R,ftemp3 ; lt \u003d bl*lt\n- FSTD ftemp3,-32(%sp)\n- XMPYU A0L,A1L,ftemp4 ; ht \u003d bh*ht\n- FSTD ftemp4,-24(%sp) ;\n-\n- LDD -8(%sp),m ; r21 \u003d m\n- LDD -16(%sp),m1 ; r19 \u003d m1\n- ADD,L m,m1,m ; m+m1\n-\n- DEPD,Z m,31,32,temp3 ; (m+m1\u003c\u003c32)\n- LDD -24(%sp),ht ; r24 \u003d ht\n-\n- CMPCLR,*\u003e\u003e\u003d m,m1,%r0 ; if (m \u003c m1)\n- ADD,L ht,high_one,ht ; ht+\u003dhigh_one\n-\n- EXTRD,U m,31,32,temp1 ; m \u003e\u003e 32\n- LDD -32(%sp),lt ; lt\n- ADD,L ht,temp1,ht ; ht+\u003d m\u003e\u003e32\n- ADD lt,temp3,lt ; lt \u003d lt+m1\n- ADD,DC ht,%r0,ht ; ht++\n-\n- ADD ht,ht,ht ; ht\u003dht+ht;\n- ADD,DC C3,%r0,C3 ; add in carry (c3++)\n-\n- ADD lt,lt,lt ; lt\u003dlt+lt;\n- ADD,DC ht,%r0,ht ; add in carry (ht++)\n-\n- ADD C1,lt,C1 ; c1\u003dc1+lt\n- ADD,DC,*NUV ht,%r0,ht ; add in carry (ht++)\n- LDO 1(C3),C3 ; bump c3 if overflow,nullify otherwise\n-\n- ADD C2,ht,C2 ; c2 \u003d c2 + ht\n- ADD,DC C3,%r0,C3 ; add in carry (c3++)\n-.endm\n-\n-;\n-;void bn_sqr_comba8(BN_ULONG *r, BN_ULONG *a)\n-; arg0 \u003d r_ptr\n-; arg1 \u003d a_ptr\n-;\n-\n-bn_sqr_comba8\n-\t.PROC\n-\t.CALLINFO FRAME\u003d128,ENTRY_GR\u003d%r3,ARGS_SAVED,ORDERING_AWARE\n-\t.EXPORT\tbn_sqr_comba8,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .ENTRY\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3\n- STD %r4,8(%sp) ; save r4\n- STD %r5,16(%sp) ; save r5\n- STD %r6,24(%sp) ; save r6\n-\n-\t;\n-\t; Zero out carries\n-\t;\n-\tCOPY %r0,c1\n-\tCOPY %r0,c2\n-\tCOPY %r0,c3\n-\n-\tLDO 128(%sp),%sp ; bump stack\n- DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L\n- DEPDI,Z 1,31,1,high_one ; Create Value 1 \u003c\u003c 32\n-\n-\t;\n-\t; Load up all of the values we are going to use\n-\t;\n- FLDD 0(a_ptr),a0 \n- FLDD 8(a_ptr),a1 \n- FLDD 16(a_ptr),a2 \n- FLDD 24(a_ptr),a3 \n- FLDD 32(a_ptr),a4 \n- FLDD 40(a_ptr),a5 \n- FLDD 48(a_ptr),a6 \n- FLDD 56(a_ptr),a7 \n-\n-\tSQR_ADD_C a0L,a0R,c1,c2,c3\n-\tSTD c1,0(r_ptr) ; r[0] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C2 a1L,a1R,a0L,a0R,c2,c3,c1\n-\tSTD c2,8(r_ptr) ; r[1] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C a1L,a1R,c3,c1,c2\n-\tSQR_ADD_C2 a2L,a2R,a0L,a0R,c3,c1,c2\n-\tSTD c3,16(r_ptr) ; r[2] \u003d c3;\n-\tCOPY %r0,c3\n-\n-\tSQR_ADD_C2 a3L,a3R,a0L,a0R,c1,c2,c3\n-\tSQR_ADD_C2 a2L,a2R,a1L,a1R,c1,c2,c3\n-\tSTD c1,24(r_ptr) ; r[3] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C a2L,a2R,c2,c3,c1\n-\tSQR_ADD_C2 a3L,a3R,a1L,a1R,c2,c3,c1\n-\tSQR_ADD_C2 a4L,a4R,a0L,a0R,c2,c3,c1\n-\tSTD c2,32(r_ptr) ; r[4] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C2 a5L,a5R,a0L,a0R,c3,c1,c2\n-\tSQR_ADD_C2 a4L,a4R,a1L,a1R,c3,c1,c2\n-\tSQR_ADD_C2 a3L,a3R,a2L,a2R,c3,c1,c2\n-\tSTD c3,40(r_ptr) ; r[5] \u003d c3;\n-\tCOPY %r0,c3\n-\n-\tSQR_ADD_C a3L,a3R,c1,c2,c3\n-\tSQR_ADD_C2 a4L,a4R,a2L,a2R,c1,c2,c3\n-\tSQR_ADD_C2 a5L,a5R,a1L,a1R,c1,c2,c3\n-\tSQR_ADD_C2 a6L,a6R,a0L,a0R,c1,c2,c3\n-\tSTD c1,48(r_ptr) ; r[6] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C2 a7L,a7R,a0L,a0R,c2,c3,c1\n-\tSQR_ADD_C2 a6L,a6R,a1L,a1R,c2,c3,c1\n-\tSQR_ADD_C2 a5L,a5R,a2L,a2R,c2,c3,c1\n-\tSQR_ADD_C2 a4L,a4R,a3L,a3R,c2,c3,c1\n-\tSTD c2,56(r_ptr) ; r[7] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C a4L,a4R,c3,c1,c2\n-\tSQR_ADD_C2 a5L,a5R,a3L,a3R,c3,c1,c2\n-\tSQR_ADD_C2 a6L,a6R,a2L,a2R,c3,c1,c2\n-\tSQR_ADD_C2 a7L,a7R,a1L,a1R,c3,c1,c2\n-\tSTD c3,64(r_ptr) ; r[8] \u003d c3;\n-\tCOPY %r0,c3\n-\n-\tSQR_ADD_C2 a7L,a7R,a2L,a2R,c1,c2,c3\n-\tSQR_ADD_C2 a6L,a6R,a3L,a3R,c1,c2,c3\n-\tSQR_ADD_C2 a5L,a5R,a4L,a4R,c1,c2,c3\n-\tSTD c1,72(r_ptr) ; r[9] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C a5L,a5R,c2,c3,c1\n-\tSQR_ADD_C2 a6L,a6R,a4L,a4R,c2,c3,c1\n-\tSQR_ADD_C2 a7L,a7R,a3L,a3R,c2,c3,c1\n-\tSTD c2,80(r_ptr) ; r[10] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C2 a7L,a7R,a4L,a4R,c3,c1,c2\n-\tSQR_ADD_C2 a6L,a6R,a5L,a5R,c3,c1,c2\n-\tSTD c3,88(r_ptr) ; r[11] \u003d c3;\n-\tCOPY %r0,c3\n-\t\n-\tSQR_ADD_C a6L,a6R,c1,c2,c3\n-\tSQR_ADD_C2 a7L,a7R,a5L,a5R,c1,c2,c3\n-\tSTD c1,96(r_ptr) ; r[12] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C2 a7L,a7R,a6L,a6R,c2,c3,c1\n-\tSTD c2,104(r_ptr) ; r[13] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C a7L,a7R,c3,c1,c2\n-\tSTD c3, 112(r_ptr) ; r[14] \u003d c3\n-\tSTD c1, 120(r_ptr) ; r[15] \u003d c1\n-\n- .EXIT\n- LDD -104(%sp),%r6 ; restore r6\n- LDD -112(%sp),%r5 ; restore r5\n- LDD -120(%sp),%r4 ; restore r4\n- BVE (%rp)\n- LDD,MB -128(%sp),%r3\n-\n-\t.PROCEND\t\n-\n-;-----------------------------------------------------------------------------\n-;\n-;void bn_sqr_comba4(BN_ULONG *r, BN_ULONG *a)\n-; arg0 \u003d r_ptr\n-; arg1 \u003d a_ptr\n-;\n-\n-bn_sqr_comba4\n-\t.proc\n-\t.callinfo FRAME\u003d128,ENTRY_GR\u003d%r3,ARGS_SAVED,ORDERING_AWARE\n-\t.EXPORT\tbn_sqr_comba4,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .entry\n-\t.align 64\n- STD %r3,0(%sp) ; save r3\n- STD %r4,8(%sp) ; save r4\n- STD %r5,16(%sp) ; save r5\n- STD %r6,24(%sp) ; save r6\n-\n-\t;\n-\t; Zero out carries\n-\t;\n-\tCOPY %r0,c1\n-\tCOPY %r0,c2\n-\tCOPY %r0,c3\n-\n-\tLDO 128(%sp),%sp ; bump stack\n- DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L\n- DEPDI,Z 1,31,1,high_one ; Create Value 1 \u003c\u003c 32\n-\n-\t;\n-\t; Load up all of the values we are going to use\n-\t;\n- FLDD 0(a_ptr),a0 \n- FLDD 8(a_ptr),a1 \n- FLDD 16(a_ptr),a2 \n- FLDD 24(a_ptr),a3 \n- FLDD 32(a_ptr),a4 \n- FLDD 40(a_ptr),a5 \n- FLDD 48(a_ptr),a6 \n- FLDD 56(a_ptr),a7 \n-\n-\tSQR_ADD_C a0L,a0R,c1,c2,c3\n-\n-\tSTD c1,0(r_ptr) ; r[0] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C2 a1L,a1R,a0L,a0R,c2,c3,c1\n-\n-\tSTD c2,8(r_ptr) ; r[1] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C a1L,a1R,c3,c1,c2\n-\tSQR_ADD_C2 a2L,a2R,a0L,a0R,c3,c1,c2\n-\n-\tSTD c3,16(r_ptr) ; r[2] \u003d c3;\n-\tCOPY %r0,c3\n-\n-\tSQR_ADD_C2 a3L,a3R,a0L,a0R,c1,c2,c3\n-\tSQR_ADD_C2 a2L,a2R,a1L,a1R,c1,c2,c3\n-\n-\tSTD c1,24(r_ptr) ; r[3] \u003d c1;\n-\tCOPY %r0,c1\n-\n-\tSQR_ADD_C a2L,a2R,c2,c3,c1\n-\tSQR_ADD_C2 a3L,a3R,a1L,a1R,c2,c3,c1\n-\n-\tSTD c2,32(r_ptr) ; r[4] \u003d c2;\n-\tCOPY %r0,c2\n-\n-\tSQR_ADD_C2 a3L,a3R,a2L,a2R,c3,c1,c2\n-\tSTD c3,40(r_ptr) ; r[5] \u003d c3;\n-\tCOPY %r0,c3\n-\n-\tSQR_ADD_C a3L,a3R,c1,c2,c3\n-\tSTD c1,48(r_ptr) ; r[6] \u003d c1;\n-\tSTD c2,56(r_ptr) ; r[7] \u003d c2;\n-\n- .EXIT\n- LDD -104(%sp),%r6 ; restore r6\n- LDD -112(%sp),%r5 ; restore r5\n- LDD -120(%sp),%r4 ; restore r4\n- BVE (%rp)\n- LDD,MB -128(%sp),%r3\n-\n-\t.PROCEND\t\n-\n-\n-;---------------------------------------------------------------------------\n-\n-MUL_ADD_C .macro A0L,A0R,B0L,B0R,C1,C2,C3\n- XMPYU A0L,B0R,ftemp1 ; m1 \u003d bl*ht\n- FSTD ftemp1,-16(%sp) ;\n- XMPYU A0R,B0L,ftemp2 ; m \u003d bh*lt\n- FSTD ftemp2,-8(%sp) ;\n- XMPYU A0R,B0R,ftemp3 ; lt \u003d bl*lt\n- FSTD ftemp3,-32(%sp)\n- XMPYU A0L,B0L,ftemp4 ; ht \u003d bh*ht\n- FSTD ftemp4,-24(%sp) ;\n-\n- LDD -8(%sp),m ; r21 \u003d m\n- LDD -16(%sp),m1 ; r19 \u003d m1\n- ADD,L m,m1,m ; m+m1\n-\n- DEPD,Z m,31,32,temp3 ; (m+m1\u003c\u003c32)\n- LDD -24(%sp),ht ; r24 \u003d ht\n-\n- CMPCLR,*\u003e\u003e\u003d m,m1,%r0 ; if (m \u003c m1)\n- ADD,L ht,high_one,ht ; ht+\u003dhigh_one\n-\n- EXTRD,U m,31,32,temp1 ; m \u003e\u003e 32\n- LDD -32(%sp),lt ; lt\n- ADD,L ht,temp1,ht ; ht+\u003d m\u003e\u003e32\n- ADD lt,temp3,lt ; lt \u003d lt+m1\n- ADD,DC ht,%r0,ht ; ht++\n-\n- ADD C1,lt,C1 ; c1\u003dc1+lt\n- ADD,DC ht,%r0,ht ; bump c3 if overflow,nullify otherwise\n-\n- ADD C2,ht,C2 ; c2 \u003d c2 + ht\n- ADD,DC C3,%r0,C3 ; add in carry (c3++)\n-.endm\n-\n-\n-;\n-;void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)\n-; arg0 \u003d r_ptr\n-; arg1 \u003d a_ptr\n-; arg2 \u003d b_ptr\n-;\n-\n-bn_mul_comba8\n-\t.proc\n-\t.callinfo FRAME\u003d128,ENTRY_GR\u003d%r3,ARGS_SAVED,ORDERING_AWARE\n-\t.EXPORT\tbn_mul_comba8,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .entry\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3\n- STD %r4,8(%sp) ; save r4\n- STD %r5,16(%sp) ; save r5\n- STD %r6,24(%sp) ; save r6\n- FSTD %fr12,32(%sp) ; save r6\n- FSTD %fr13,40(%sp) ; save r7\n-\n-\t;\n-\t; Zero out carries\n-\t;\n-\tCOPY %r0,c1\n-\tCOPY %r0,c2\n-\tCOPY %r0,c3\n-\n-\tLDO 128(%sp),%sp ; bump stack\n- DEPDI,Z 1,31,1,high_one ; Create Value 1 \u003c\u003c 32\n-\n-\t;\n-\t; Load up all of the values we are going to use\n-\t;\n- FLDD 0(a_ptr),a0 \n- FLDD 8(a_ptr),a1 \n- FLDD 16(a_ptr),a2 \n- FLDD 24(a_ptr),a3 \n- FLDD 32(a_ptr),a4 \n- FLDD 40(a_ptr),a5 \n- FLDD 48(a_ptr),a6 \n- FLDD 56(a_ptr),a7 \n-\n- FLDD 0(b_ptr),b0 \n- FLDD 8(b_ptr),b1 \n- FLDD 16(b_ptr),b2 \n- FLDD 24(b_ptr),b3 \n- FLDD 32(b_ptr),b4 \n- FLDD 40(b_ptr),b5 \n- FLDD 48(b_ptr),b6 \n- FLDD 56(b_ptr),b7 \n-\n-\tMUL_ADD_C a0L,a0R,b0L,b0R,c1,c2,c3\n-\tSTD c1,0(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a0L,a0R,b1L,b1R,c2,c3,c1\n-\tMUL_ADD_C a1L,a1R,b0L,b0R,c2,c3,c1\n-\tSTD c2,8(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a2L,a2R,b0L,b0R,c3,c1,c2\n-\tMUL_ADD_C a1L,a1R,b1L,b1R,c3,c1,c2\n-\tMUL_ADD_C a0L,a0R,b2L,b2R,c3,c1,c2\n-\tSTD c3,16(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a0L,a0R,b3L,b3R,c1,c2,c3\n-\tMUL_ADD_C a1L,a1R,b2L,b2R,c1,c2,c3\n-\tMUL_ADD_C a2L,a2R,b1L,b1R,c1,c2,c3\n-\tMUL_ADD_C a3L,a3R,b0L,b0R,c1,c2,c3\n-\tSTD c1,24(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a4L,a4R,b0L,b0R,c2,c3,c1\n-\tMUL_ADD_C a3L,a3R,b1L,b1R,c2,c3,c1\n-\tMUL_ADD_C a2L,a2R,b2L,b2R,c2,c3,c1\n-\tMUL_ADD_C a1L,a1R,b3L,b3R,c2,c3,c1\n-\tMUL_ADD_C a0L,a0R,b4L,b4R,c2,c3,c1\n-\tSTD c2,32(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a0L,a0R,b5L,b5R,c3,c1,c2\n-\tMUL_ADD_C a1L,a1R,b4L,b4R,c3,c1,c2\n-\tMUL_ADD_C a2L,a2R,b3L,b3R,c3,c1,c2\n-\tMUL_ADD_C a3L,a3R,b2L,b2R,c3,c1,c2\n-\tMUL_ADD_C a4L,a4R,b1L,b1R,c3,c1,c2\n-\tMUL_ADD_C a5L,a5R,b0L,b0R,c3,c1,c2\n-\tSTD c3,40(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a6L,a6R,b0L,b0R,c1,c2,c3\n-\tMUL_ADD_C a5L,a5R,b1L,b1R,c1,c2,c3\n-\tMUL_ADD_C a4L,a4R,b2L,b2R,c1,c2,c3\n-\tMUL_ADD_C a3L,a3R,b3L,b3R,c1,c2,c3\n-\tMUL_ADD_C a2L,a2R,b4L,b4R,c1,c2,c3\n-\tMUL_ADD_C a1L,a1R,b5L,b5R,c1,c2,c3\n-\tMUL_ADD_C a0L,a0R,b6L,b6R,c1,c2,c3\n-\tSTD c1,48(r_ptr)\n-\tCOPY %r0,c1\n-\t\n-\tMUL_ADD_C a0L,a0R,b7L,b7R,c2,c3,c1\n-\tMUL_ADD_C a1L,a1R,b6L,b6R,c2,c3,c1\n-\tMUL_ADD_C a2L,a2R,b5L,b5R,c2,c3,c1\n-\tMUL_ADD_C a3L,a3R,b4L,b4R,c2,c3,c1\n-\tMUL_ADD_C a4L,a4R,b3L,b3R,c2,c3,c1\n-\tMUL_ADD_C a5L,a5R,b2L,b2R,c2,c3,c1\n-\tMUL_ADD_C a6L,a6R,b1L,b1R,c2,c3,c1\n-\tMUL_ADD_C a7L,a7R,b0L,b0R,c2,c3,c1\n-\tSTD c2,56(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a7L,a7R,b1L,b1R,c3,c1,c2\n-\tMUL_ADD_C a6L,a6R,b2L,b2R,c3,c1,c2\n-\tMUL_ADD_C a5L,a5R,b3L,b3R,c3,c1,c2\n-\tMUL_ADD_C a4L,a4R,b4L,b4R,c3,c1,c2\n-\tMUL_ADD_C a3L,a3R,b5L,b5R,c3,c1,c2\n-\tMUL_ADD_C a2L,a2R,b6L,b6R,c3,c1,c2\n-\tMUL_ADD_C a1L,a1R,b7L,b7R,c3,c1,c2\n-\tSTD c3,64(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a2L,a2R,b7L,b7R,c1,c2,c3\n-\tMUL_ADD_C a3L,a3R,b6L,b6R,c1,c2,c3\n-\tMUL_ADD_C a4L,a4R,b5L,b5R,c1,c2,c3\n-\tMUL_ADD_C a5L,a5R,b4L,b4R,c1,c2,c3\n-\tMUL_ADD_C a6L,a6R,b3L,b3R,c1,c2,c3\n-\tMUL_ADD_C a7L,a7R,b2L,b2R,c1,c2,c3\n-\tSTD c1,72(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a7L,a7R,b3L,b3R,c2,c3,c1\n-\tMUL_ADD_C a6L,a6R,b4L,b4R,c2,c3,c1\n-\tMUL_ADD_C a5L,a5R,b5L,b5R,c2,c3,c1\n-\tMUL_ADD_C a4L,a4R,b6L,b6R,c2,c3,c1\n-\tMUL_ADD_C a3L,a3R,b7L,b7R,c2,c3,c1\n-\tSTD c2,80(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a4L,a4R,b7L,b7R,c3,c1,c2\n-\tMUL_ADD_C a5L,a5R,b6L,b6R,c3,c1,c2\n-\tMUL_ADD_C a6L,a6R,b5L,b5R,c3,c1,c2\n-\tMUL_ADD_C a7L,a7R,b4L,b4R,c3,c1,c2\n-\tSTD c3,88(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a7L,a7R,b5L,b5R,c1,c2,c3\n-\tMUL_ADD_C a6L,a6R,b6L,b6R,c1,c2,c3\n-\tMUL_ADD_C a5L,a5R,b7L,b7R,c1,c2,c3\n-\tSTD c1,96(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a6L,a6R,b7L,b7R,c2,c3,c1\n-\tMUL_ADD_C a7L,a7R,b6L,b6R,c2,c3,c1\n-\tSTD c2,104(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a7L,a7R,b7L,b7R,c3,c1,c2\n-\tSTD c3,112(r_ptr)\n-\tSTD c1,120(r_ptr)\n-\n- .EXIT\n- FLDD -88(%sp),%fr13 \n- FLDD -96(%sp),%fr12 \n- LDD -104(%sp),%r6 ; restore r6\n- LDD -112(%sp),%r5 ; restore r5\n- LDD -120(%sp),%r4 ; restore r4\n- BVE (%rp)\n- LDD,MB -128(%sp),%r3\n-\n-\t.PROCEND\t\n-\n-;-----------------------------------------------------------------------------\n-;\n-;void bn_mul_comba4(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)\n-; arg0 \u003d r_ptr\n-; arg1 \u003d a_ptr\n-; arg2 \u003d b_ptr\n-;\n-\n-bn_mul_comba4\n-\t.proc\n-\t.callinfo FRAME\u003d128,ENTRY_GR\u003d%r3,ARGS_SAVED,ORDERING_AWARE\n-\t.EXPORT\tbn_mul_comba4,ENTRY,PRIV_LEV\u003d3,NO_RELOCATION,LONG_RETURN\n- .entry\n-\t.align 64\n-\n- STD %r3,0(%sp) ; save r3\n- STD %r4,8(%sp) ; save r4\n- STD %r5,16(%sp) ; save r5\n- STD %r6,24(%sp) ; save r6\n- FSTD %fr12,32(%sp) ; save r6\n- FSTD %fr13,40(%sp) ; save r7\n-\n-\t;\n-\t; Zero out carries\n-\t;\n-\tCOPY %r0,c1\n-\tCOPY %r0,c2\n-\tCOPY %r0,c3\n-\n-\tLDO 128(%sp),%sp ; bump stack\n- DEPDI,Z 1,31,1,high_one ; Create Value 1 \u003c\u003c 32\n-\n-\t;\n-\t; Load up all of the values we are going to use\n-\t;\n- FLDD 0(a_ptr),a0 \n- FLDD 8(a_ptr),a1 \n- FLDD 16(a_ptr),a2 \n- FLDD 24(a_ptr),a3 \n-\n- FLDD 0(b_ptr),b0 \n- FLDD 8(b_ptr),b1 \n- FLDD 16(b_ptr),b2 \n- FLDD 24(b_ptr),b3 \n-\n-\tMUL_ADD_C a0L,a0R,b0L,b0R,c1,c2,c3\n-\tSTD c1,0(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a0L,a0R,b1L,b1R,c2,c3,c1\n-\tMUL_ADD_C a1L,a1R,b0L,b0R,c2,c3,c1\n-\tSTD c2,8(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a2L,a2R,b0L,b0R,c3,c1,c2\n-\tMUL_ADD_C a1L,a1R,b1L,b1R,c3,c1,c2\n-\tMUL_ADD_C a0L,a0R,b2L,b2R,c3,c1,c2\n-\tSTD c3,16(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a0L,a0R,b3L,b3R,c1,c2,c3\n-\tMUL_ADD_C a1L,a1R,b2L,b2R,c1,c2,c3\n-\tMUL_ADD_C a2L,a2R,b1L,b1R,c1,c2,c3\n-\tMUL_ADD_C a3L,a3R,b0L,b0R,c1,c2,c3\n-\tSTD c1,24(r_ptr)\n-\tCOPY %r0,c1\n-\n-\tMUL_ADD_C a3L,a3R,b1L,b1R,c2,c3,c1\n-\tMUL_ADD_C a2L,a2R,b2L,b2R,c2,c3,c1\n-\tMUL_ADD_C a1L,a1R,b3L,b3R,c2,c3,c1\n-\tSTD c2,32(r_ptr)\n-\tCOPY %r0,c2\n-\n-\tMUL_ADD_C a2L,a2R,b3L,b3R,c3,c1,c2\n-\tMUL_ADD_C a3L,a3R,b2L,b2R,c3,c1,c2\n-\tSTD c3,40(r_ptr)\n-\tCOPY %r0,c3\n-\n-\tMUL_ADD_C a3L,a3R,b3L,b3R,c1,c2,c3\n-\tSTD c1,48(r_ptr)\n-\tSTD c2,56(r_ptr)\n-\n- .EXIT\n- FLDD -88(%sp),%fr13 \n- FLDD -96(%sp),%fr12 \n- LDD -104(%sp),%r6 ; restore r6\n- LDD -112(%sp),%r5 ; restore r5\n- LDD -120(%sp),%r4 ; restore r4\n- BVE (%rp)\n- LDD,MB -128(%sp),%r3\n-\n-\t.PROCEND\t\n-\n-\n-\t.SPACE\t$TEXT$\n-\t.SUBSPA\t$CODE$\n-\t.SPACE\t$PRIVATE$,SORT\u003d16\n-\t.IMPORT\t$global$,DATA\n-\t.SPACE\t$TEXT$\n-\t.SUBSPA\t$CODE$\n-\t.SUBSPA\t$LIT$,ACCESS\u003d0x2c\n-C$4\n-\t.ALIGN\t8\n-\t.STRINGZ\t\u0022Division would overflow (%d)\u005cn\u0022\n-\t.END\ndiff --git a/crypto/bn/build.info b/crypto/bn/build.info\nindex 3544106..dbb4196 100644\n--- a/crypto/bn/build.info\n+++ b/crypto/bn/build.info\n@@ -65,14 +65,3 @@ INCLUDE[armv4-mont.o]\u003d..\n GENERATE[armv4-gf2m.S]\u003dasm/armv4-gf2m.pl $(PERLASM_SCHEME)\n INCLUDE[armv4-gf2m.o]\u003d..\n GENERATE[armv8-mont.S]\u003dasm/armv8-mont.pl $(PERLASM_SCHEME)\n-\n-OVERRIDES\u003dpa-risc2W.o pa-risc2.c\n-BEGINRAW[Makefile]\n-# GNU assembler fails to compile PA-RISC2 modules, insist on calling\n-# vendor assembler...\n-{- $builddir -}/pa-risc2W.o: {- $sourcedir -}/asm/pa-risc2W.s\n-\tCC\u003d\u0022$(CC)\u0022 $(PERL) $(SRCDIR)/util/fipsas.pl $(SRCDIR) $\u003c /usr/ccs/bin/as -o pa-risc2W.o {- $sourcedir -}/asm/pa-risc2W.s\n-{- $builddir -}/pa-risc2.o: {- $sourcedir -}/asm/pa-risc2.s\n-\tCC\u003d\u0022$(CC)\u0022 $(PERL) $(SRCDIR)/util/fipsas.pl $(SRCDIR) $\u003c /usr/ccs/bin/as -o pa-risc2.o {- $sourcedir -}/asm/pa-risc2.s\n-\n-ENDRAW[Makefile]\n","s":{"c":1752651711,"u": 31300}} ],"g": 40570,"chitpc": 0,"ehitpc": 0,"indexed":0 , "ab": 0, "si": 0, "db":0, "di":0, "sat":0, "lfc": "0000"}